View 64M16_4704381.PDF datasheet online --- IC-ON-LINE

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products and specifications discussed herein ar e subject to change by micron without notice. 1gb: x4, x8, x16 ddr3 sdram features pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_d1 .fm - rev. d 8/1/08 en 1 ?2006 micron technology, inc. all rights reserved. ddr3 sdram mt41j256m4 ? 32 me g x 4 x 8 banks mt41j128m8 ? 16 me g x 8 x 8 banks mt41j64M16 ? 8 meg x 16 x 8 banks features ?v dd = v dd q = +1.5v 0.075v ? 1.5v center-terminated push/pull i/o ? differential bidirectional data strobe ?8 n -bit prefetch architecture ? differential clock inputs (ck, ck#) ?8 internal banks ? nominal and dynamic on-die termination (odt) for data, strobe, and mask signals ? cas (read) latency (cl): 5, 6, 7, 8, 9, 10, or 11 ? posted cas additive latency (al): 0, cl - 1, cl - 2 ? cas (write) latency (cwl): 5, 6, 7, 8, based on t ck ? fixed burst length (bl) of 8 and burst chop (bc) of 4 (via the mode register set [mrs]) ? selectable bc4 or bl8 on-the-fly (otf) ? self refresh mode ?t c of 0 o c to 95 o c ? 64ms, 8,192 cycle refresh at 0 o c to 85 o c ? 32ms at 85 o c to 95 o c ? clock frequency range of 300?800 mhz ? self refresh temperature (srt) ?automatic self refresh (asr) ? write leveling ?multipurpose register ? output driver calibration options marking ? configuration ? 256 meg x 4 256m4 ? 128 meg x 8 128m8 ? 64 meg x 16 64M16 ? fbga package (pb-free) - x4, x8 ? 78-ball fbga (8mm x 11.5mm) rev. f jp ? 78-ball fbga (9mm x 11.5mm) rev. d hx ? 86-ball fbga (9mm x 15.5mm) rev. b by ? fbga package (pb-free) - x16 ? 96-ball fbga (9mm x 15.5mm) rev. b la ? timing - cycle time ? 1.25ns @ cl = 11 (ddr3-1600) -125 ? 1.25ns @ cl = 10 (ddr3-1600) -125e ? 1.25ns @ cl = 9 (ddr3-1600) -125f ? 1.5ns @ cl = 10 (ddr3-1333) -15 ? 1.5ns @ cl = 9 (ddr3-1333) -15e ? 1.5ns @ cl = 8 (ddr3-1333) -15f ? 1.87ns @ cl = 8 (ddr3-1066) -187 ? 1.87ns @ cl = 7 (ddr3-1066) -187e ? 2.5ns @ cl = 6 (ddr3-800) -25 ? 2.5ns @ cl = 5 (ddr3-800) -25e ? revision :b/:d/:f table 1: key timing parameters speed grade data rate (mt/s) ta r g et t rcd- t rp-cl t rcd (ns) t rp (ns) cl (ns) -125 1600 11-11-11 13.75 13.75 13.75 -125e 1600 10-10-10 12.5 12.5 12.5 -125f 1600 9-9-9 11.25 11.25 11.25 -15 1333 10-10-10 15 15 15 -15e 1333 9-9-9 13.5 13.5 13.5 -15f 1333 8-8-8 12 12 12 -187 1066 8-8-8 15 15 15 -187e 1066 7-7-7 13.1 13.1 13.1 -25 800 6-6-6 15 15 15 -25e 800 5-5-5 12.5 12.5 12.5
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_d1 .fm - rev. d 8/1/08 en 2 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram features figure 1: 1gb ddr3 part numbers fbga part marking decoder due to space limitations, fbga-packaged components have an abbreviated part marking that is different from the part number. for a quick conversion of an fbga code, see the fbga part marking decoder on micron?s web site: www.micron.com . table 2: addressing parameter 256 meg x 4 128 meg x 8 64 meg x 16 configuration 32 meg x 4 x 8 banks 16 meg x 8 x 8 banks 8 meg x 16 x 8 banks refresh count 8k 8k 8k row addressing 16k (a[13:0]) 16k (a[13:0]) 8k (a[12:0]) bank addressing 8 (ba[2:0]) 8 (ba[2:0]) 8 (ba[2:0]) column addressing 2k (a[11, 9:0]) 1k (a[9:0]) 1k (a[9:0]) package 78-ball 8mm x 11.5mm fbga 78-ball 9mm x 11.5mm fbga 86-ball 9mm x 15.5mm fbga 96-ball 9mm x 15.5mm fbga mark jp hx by la rev. f d b b example part number: mt41j256m4by-15:b configuration 256 meg x 4 128 meg x 8 64 meg x 16 256m4 128m8 64M16 speed grade t ck = 1.25ns, cl = 11 t ck = 1.25ns, cl = 10 t ck = 1.25ns, cl = 9 t ck = 1.5ns, cl = 10 t ck = 1.5ns, cl = 9 t ck = 1.5ns, cl = 8 t ck = 1.87ns, cl = 8 t ck = 1.87ns, cl = 7 t ck = 2.5ns, cl = 6 t ck = 2.5ns, cl = 5 -125 -125e -125f -15 -15e -15f -187 -187e -25 -25e - configuration mt41j package speed revision revision :b/:d/:f : temperature commercial industrial temperature { none it
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_toc.fm - rev. d 8/1/08 en 3 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram table of contents table of contents state diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 general notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 functional block diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 ball assignments and descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 absolute ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 input/output capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 electrical specifications ? i dd specifications and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 electrical characteristics ? i dd specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 electrical specifications ? dc and ac. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 input operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 ac overshoot/undershoot specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 slew rate definitions for single-ended input signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 slew rate definitions for differential input signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 odt characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 odt resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 odt sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 odt timing definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 output driver impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 34 output driver impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 34 driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 34 driver output sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 alternative 40 driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 40 driver output sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 output characteristics and operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 reference output load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 slew rate definitions for single-ended output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 slew rate definitions for differential output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 speed bin tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 command and address setup, hold, and derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 data setup, hold, and derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 truth tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 deselect (des) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 no operation (nop). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 zq calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 activate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 self refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 dll disable mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 input clock frequency change. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 write leveling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_toc.fm - rev. d 8/1/08 en 4 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram table of contents initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 mode register 0 (mr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 mode register 1 (mr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 mode register 2 (mr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 mode register 3 (mr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 mode register set (mrs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 zq calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 activate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 self refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 extended temperature usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 on-die termination (odt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 functional representation of odt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 nominal odt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 dynamic odt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 synchronous odt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 odt off during reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 asynchronous odt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 synchronous to asynchronous odt mode tran sition (power-down entry). . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 asynchronous to synchronous odt mode transition (power-down ex it) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_lof.fm - rev. d 8/1/08 en 5 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram list of figures list of figures figure 1: 1gb ddr3 part numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 figure 2: simplified state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 figure 3: 256 meg x 4 functional block diag ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 figure 4: 128 meg x 8 functional block diag ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 5: 64 meg x 16 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 6: 78-ball fbga ? x4, x8 ball assi gnments (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 7: 86-ball fbga ? x4, x8 ball assi gnments (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 figure 8: 96-ball fbga ? x16 ball assignments (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 figure 9: 78-ball fbga ? x4, x8; ?jp? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 10: 78-ball fbga ? x4, x8; ?hx? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 11: 86-ball fbga ? x4, x8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 12: 96-ball fbga ? x16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 13: thermal measurement po int . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 14: i dd 1 example ? ddr3-800, 5-5-5, x8 (-25e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 figure 15: i dd 2n/i dd 3n example ? ddr3-800, 5-5-5, x8 (-25e). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 figure 16: i dd 4r example ? ddr3-800, 5-5-5, x8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 figure 17: input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 figure 18: overshoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 figure 19: undershoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 figure 20: single-ended requirements for differential signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 figure 21: definition of differential ac-swing and t dvac. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 figure 22: nominal slew rate definition fo r single-ended input signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 figure 23: nominal differential input slew rate definition fo r dqs, dqs# and ck, ck# . . . . . . . . . . . . . . . . . .48 figure 24: odt levels and i-v characterist ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 figure 25: odt timing reference load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 figure 26: t aon and t aof definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 figure 27: t aonpd and t aofpd definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 figure 28: t adc definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 figure 29: output driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 figure 30: dq output signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 figure 31: differential output signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 figure 32: reference output load for ac timing and output slew rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 figure 33: nominal slew rate definition fo r single-ended output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 figure 34: nominal differential output slew rate definition for dqs, dqs# . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 figure 35: nominal slew rate and t vac for t is (command and address ? clock) . . . . . . . . . . . . . . . . . . . . . . . . .80 figure 36: nominal slew rate for t ih (command and address ? clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 figure 37: tangent line for t is (command and address ? clock). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 figure 38: tangent line for t ih (command and address ? clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 figure 39: nominal slew rate and t vac for t ds (dq ? strobe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 figure 40: nominal slew rate for t dh (dq ? strobe). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 figure 41: tangent line for t ds (dq ? strobe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 figure 42: tangent line for t dh (dq ? strobe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 figure 43: refresh mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 figure 44: dll enable mode to dll disable mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 figure 45: dll disable mode to dll enable mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 figure 46: dll disable t dqsck timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 figure 47: change frequency during precharge power-down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 48: write leveling concep t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 figure 49: write leveling sequen ce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 figure 50: exit write leveling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 51: initialization sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 52: mrs-to-mrs command timing ( t mrd). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 53: mrs-to-nonmrs command timing ( t mod). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 54: mode register 0 (mr0) definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure 55: read latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 56: mode register 1 (mr1) definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_lof.fm - rev. d 8/1/08 en 6 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram list of figures figure 57: read latency (al = 5, cl = 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 figure 58: mode register 2 (mr2) definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 figure 59: cas write latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 figure 60: mode register 3 (mr3) definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 figure 61: multipurpose register (mpr) bloc k diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 figure 62: mpr system read calibration with bl8: fixed burst order single readout. . . . . . . . . . . . . . . . . . . 122 figure 63: mpr system read calibration with bl8: fixed bu rst order, back-to-back readout . . . . . . . . . . . 123 figure 64: mpr system read calibration with bc4: lower nibb le, then upper nibble. . . . . . . . . . . . . . . . . . 124 figure 65: mpr system read calibration with bc4: upper nibb le, then lower nibble. . . . . . . . . . . . . . . . . . 125 figure 66: zq calibration timing (zqcl and zqcs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 figure 67: example: meeting t rrd (min) and t rcd (min) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 figure 68: example: t faw. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 figure 69: read latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 figure 70: consecutive read bursts (bl8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 figure 71: consecutive read bursts (bc4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 figure 72: nonconsecutive read bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 figure 73: read (bl8) to write (bl8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 figure 74: read (bc4) to write (bc4) otf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 figure 75: read to precharge (bl8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 figure 76: read to precharge (bc4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 figure 77: read to precharge (al = 5, cl = 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 figure 78: read with auto precha rge (al = 4, cl = 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 figure 79: data output timing ? t dqsq and data valid window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 figure 80: data strobe timing ? reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 figure 81: method for calculating t lz and t hz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 figure 82: t rpre timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 figure 83: t rpst timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 figure 84: t wpre timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 figure 85: t wpst timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 figure 86: write burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 figure 87: consecutive write (bl8) to write (bl8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 figure 88: consecutive write (bc4) to write (bc4) via mrs or otf. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 figure 89: nonconsecutive write to write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 figure 90: write (bl8) to read (bl8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 figure 91: write to read (bc4 mode regist er setting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 figure 92: write (bc4 otf) to read (bc4 otf) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 figure 93: write (bl8) to precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 figure 94: write (bc4 mode register settin g) to precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 figure 95: write (bc4 otf) to precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 figure 96: data input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 figure 97: self refresh entry/exit timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 figure 98: active power-down entry and exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 figure 99: precharge power-down (fast-exit mode) entry and exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 figure 100: precharge power-down (slow-exit mode) entry and exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 figure 101: power-down entry after read or read with auto pr echarge (rdap) . . . . . . . . . . . . . . . . . . . . . . . 154 figure 102: power-down entry after write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 figure 103: power-down entry after write wi th auto precharge (wrap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 figure 104: refresh to power-down entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 figure 105: activate to power-down entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 figure 106: precharge to power-down entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 figure 107: mrs command to power-down entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 figure 108: power-down exit to refresh to power-down entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 figure 109: reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 figure 110: on-die termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 figure 111: dynamic odt: odt asserted before and after the write, bc4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 64 figure 112: dynamic odt: without write command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_lof.fm - rev. d 8/1/08 en 7 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram list of figures figure 113: dynamic odt: odt pin asserted together wi th write command for 6 clock cycles, bl8 . . . . 165 figure 114: dynamic odt: odt pin assert ed with write command for 6 clock cycles, bc4. . . . . . . . . . . . . 166 figure 115: dynamic odt: odt pin assert ed with write command for 4 clock cycles, bc4. . . . . . . . . . . . . 166 figure 116: synchronous odt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 figure 117: synchronous odt (bc4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 figure 118: odt during reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 figure 119: asynchronous odt timi ng with fast odt transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 figure 120: synchronous to asynchrono us transition during precharge power-down (dll off) entry . . . . 175 figure 121: asynchronous to synchronou s transition during precharge power- down (dll off) exit. . . . . . 177 figure 122: transition period for short cke low cycles with entry and exit pe riod overlapping . . . . . . . . . 179 figure 123: transition period for short cke high cycles with entry and exit pe riod overlapping. . . . . . . . . 180
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_lot.fm - rev. d 8/1/08 en 8 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram list of tables list of tables table 1: key timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 2: addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 table 3: 78-ball fbga ? x4, x8 ball descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 table 4: 86-ball fbga ? x4, x8 ball descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 table 5: 96-ball fbga ? x16 ball descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 table 6: absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 table 7: input/output capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 table 8: thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 table 9: i dd measurement conditions reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 table 10: definition of switching for command and address input signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 table 11: definition of switching for data pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 table 12: timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 table 13: i dd measurement conditions for i dd 0 and i dd 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 table 14: i dd measurement conditions for power-down currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 table 15: i dd measurement conditions for i dd 4r, i dd 4w. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 table 16: i dd measurement conditions for i dd 5b, i dd 6, i dd 6et . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 table 17: i dd measurement conditions for i dd 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 table 18: i dd 7 patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 table 19: i dd maximum limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 table 20: dc electrical characteristics and operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 table 21: dc electrical characteristics and input conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 table 22: ac input operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 table 23: control and address pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 table 24: clock, data, strobe, and mask pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 table 25: differential input operating conditions (ck, ck# and dq s, dqs#) . . . . . . . . . . . . . . . . . . . . . . . . . . .4 4 table 26: allowed time before ringback ( t dvac) for ck - ck# and dqs - dqs#. . . . . . . . . . . . . . . . . . . . . . . . .45 table 27: single-ended input slew rate definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 table 28: differential input slew rate definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 table 29: on-die termination dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 table 30: r tt effective impedances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 table 31: odt sensitivity definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 table 32: odt temperature and voltage sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 table 33: odt timing definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 table 34: reference settings for od t timing measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 table 35: 34 driver impedance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 table 36: 34 driver pull-up and pull-down impedance calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 table 37: 34 driver i oh /i ol characteristics: v dd = v dd q = 1.5v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 table 38: 34 driver i oh /i ol characteristics: v dd = v dd q = 1.575v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 table 39: 34 driver i oh /i ol characteristics: v dd = v dd q = 1.425v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 table 40: 34 output driver sensitivity definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 table 41: 34 output driver voltage and temperature sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 table 42: 40 driver impedance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 table 43: 40 output driver sensitivity definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 table 44: 40 output driver voltage and temperature sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 table 45: single-ended output driver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 table 46: differential output driver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 table 47: single-ended output slew rate definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 table 48: differential output slew rate definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 table 49: ddr3-800 speed bins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 table 50: ddr3-1066 speed bins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 table 51: ddr3-1333 speed bins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_lot.fm - rev. d 8/1/08 en 9 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram list of tables table 52: ddr3-1600 speed bins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 table 54: command and address setup and hold values refere nced at 1 v/ns ? ac/dc-based . . . . . . . . . . .77 table 55: ddr3-800, ddr3-1066, ddr3-1333, and ddr3-1600 derating values for t is/ t ih ? ac/dc-based78 table 56: ddr3-1333 and ddr3-1600 derating values for t is/ t ih ? ac/dc-based . . . . . . . . . . . . . . . . . . . . . . .78 table 57: minimum required time t vac above v ih ( ac ) for valid transition . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 table 58: data setup and hold values at 1 v/ns (dqs, dqs# at 2 v/ns) ? ac/dc-based . . . . . . . . . . . . . . . . . .84 table 59: ddr3-800, ddr3-1066, ddr3-1333, and ddr3-1600 derating values for t ds/ t dh ? ac/dc-based85 table 60: ddr3-1333and ddr3-1600 derating values for t ds/ t dh ? ac/dc-based . . . . . . . . . . . . . . . . . . . . .85 table 61: required time t vac above v ih ( ac ) (below v il [ ac ]) for valid transition. . . . . . . . . . . . . . . . . . . . . . . .86 table 62: truth table ? command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 table 63: truth table ? cke. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 table 64: read command summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 table 65: write command summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 table 66: read electrical characte ristics, dll disable mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 table 67: write leveling matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 68: burst order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 69: mpr functional description of mr3 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 70: mpr readouts and burst order bit mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 table 71: self refresh temperature and auto self refresh descript ion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 table 72: self refresh mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 table 73: command to power-down entry parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 table 74: power-down modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 table 75: truth table ? odt (nominal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 table 76: odt parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 table 77: dynamic odt specific parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 table 78: mode registers for rtt_nom. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 table 79: mode registers for rtt_wr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 table 80: timing diagrams for dynamic odt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 table 81: synchronous odt parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 table 83: odt parameters for power-down (d ll off) entry and exit transition period . . . . . . . . . . . . . . . . 175
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_d2.fm - rev. d 8/1/08 en 10 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram state diagram state diagram figure 2: simplified state diagram s rx = s elf refresh exit write = wr, wr s 4, wr s 8 write ap = wrap, wrap s 4, wrap s 8 zq c l = zq lon g c alibration zq cs = zq s hort c alibration bank a c tive rea d in g writin g a c tivatin g refreshin g s elf refresh i d le a c tive power- d own zq c ali b ration from any state power applie d reset pro c e d ure power on initialization mr s , mpr, write levelin g pre c har g e power- d own writin g rea d in g automati c sequen c e c omman d sequen c e pre c har g in g read read read read ap read ap read ap pre, prea pre, prea pre, prea write write c ke l c ke l c ke l write write ap write ap write ap pde pde pdx pdx s rx s re ref mr s a c t re s et zq c l zq c l/zq cs a c t = a c tivate mpr = multipurpose re g ister mr s = mo d e re g ister set pde = power- d own entry pdx = power- d own exit pre = pre c har g e prea = pre c har g e all read = rd, rd s 4, rd s 8 read ap = rdap, rdap s 4, rdap s 8 ref = refre s h re s et = s tart re s et pro c edure s re = s elf refresh entry
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_d2.fm - rev. d 8/1/08 en 11 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram functional description functional description the ddr3 sdram uses a double data rate architecture to achieve high-speed operation. the double data rate architecture is an 8 n -prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the ddr3 sdram consists of a single 8 n -bit-wide, one-clock-cycle data transfer at the internal dram core and eight corresponding n -bit-wide, one-half-clock- cycle data transfers at the i/o pins. the differential data strobe (dqs, dqs#) is transmitted externally, along with data, for use in data capture at the ddr3 sdram input receiver. dqs is center-aligned with data for writes. the read data is transmitted by the ddr3 sdram and edge-aligned to the data strobes. the ddr3 sdram operates from a differentia l clock (ck and ck#). the crossing of ck going high and ck# going low is referred to as the positive edge of ck. control, command, and address signals are registered at every positive edge of ck. input data is registered on the first rising edge of dqs after the write preamble, and output data is referenced on the first rising edge of dqs after the read preamble. read and write accesses to the ddr3 sdram are burst-oriented. a ccesses start at a selected location and continue for a prog rammed number of locations in a programmed sequence. accesses begin with the registration of an activate command, which is then followed by a read or write command. the address bits registered coincident with the activate command are used to select the bank and row to be accessed. the address bits registered coincident with the read or write commands are used to select the bank and the starting column location for the burst access. ddr3 sdram use read and write bl8 and bc 4. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. as with standard ddr sdram, the pipeline d, multibank architecture of ddr3 sdram allows for concurrent operation, thereby providing high bandwidth by hiding row precharge and activation time. a self refresh mode is provided, along with a power-saving, power-down mode. general notes ? the functionality and the timi ng specifications discussed in this data sheet are for the dll enable mode of operation (normal operation). ? throughout the data sheet, the various figures and text refer to dqs as ?dq.? the dq term is to be interpreted as any and all dq collectively, unless specifically stated otherwise. ? the terms ?dqs? and ?ck? found throughout the data sheet are to be interpreted as dqs, dqs# and ck, ck# respectively, un less specifically stated otherwise. ? complete functionality may be described throughout the entire document, and any page or diagram may have been simplified to convey a topic and may not be inclusive of all requirements. ? any specific requirement takes precedence over a general statement. ? any functionality not specifically stated herewithin is considered undefined, illegal, and not supported and can result in unknown operation. ? row addressing is denoted as a[ n :0] ( 1gb: n = 12 [x16]; 1gb: n = 13 [x4, x8]).
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_d2.fm - rev. d 8/1/08 en 12 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram functional block diagrams functional block diagrams ddr3 sdram is a high-speed, cmos dynamic random access memory. it is internally configured as an 8-bank dram. figure 3: 256 meg x 4 functional block diagram bank 5 bank 6 bank 7 bank 4 bank 7 bank 4 bank 5 bank 6 14 row- a dd ress mux c ontrol lo g i c c olumn- a dd ress c ounter/ lat c h mo d e re g isters 11 c omman d d e c o d e a[13:0] ba[2:0] 14 a dd ress re g ister 17 25 6 (x32) 8,192 i/o g atin g dm mask lo g i c c olumn d e c o d er bank 0 memory array (1 6 ,384 x 25 6 x 32) bank 0 row- a dd ress lat c h an d d e c o d er 1 6 ,384 s ense amplifiers bank c ontrol lo g i c 1 6 bank 1 bank 2 bank 3 14 8 3 3 refresh c ounter 4 32 32 32 dq s , dq s # c olumns 0, 1, an d 2 c olumns 0, 1, an d 2 zq c l, zq cs to pull-up/pull- d own networks read d rivers dq[3:0] read fifo an d d ata mux data 4 3 bank 1 bank 2 bank 3 dm dm c k, c k# dq s , dq s # zq c al cs # zq rzq c k, c k# ra s # we# c a s # odt c ke re s et# c k, c k# dll dq[3:0] (1 . . . 4) (1, 2) sw1 sw2 v dd q/2 r tt _ nom r tt _ wr sw1 sw2 v dd q/2 r tt _ nom r tt _ wr sw1 sw2 v dd q/2 r tt _ nom r tt _ wr otf b c 4 ( b urst c hop) b c 4 c olumn 2 (sele c t upper or lower ni bb le for b c 4) data interfa c e write d rivers an d input lo g i c odt c ontrol v ss q a12 otf b c 4
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_d2.fm - rev. d 8/1/08 en 13 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram functional block diagrams figure 4: 128 meg x 8 functional block diagram figure 5: 64 meg x 16 functional block diagram bank 5 bank 6 bank 7 bank 4 bank 7 bank 4 bank 5 bank 6 14 row- a dd ress mux c ontrol lo g i c c olumn- a dd ress c ounter/ lat c h mo d e re g isters 10 c omman d d e c o d e a[13:0] ba[2:0] 14 a dd ress re g ister 17 8,192 i/o g atin g dm mask lo g i c c olumn d e c o d er bank 0 memory array (1 6 ,384 x 128 x 6 4) bank 0 row- a dd ress lat c h an d d e c o d er 1 6 ,384 s ense amplifiers bank c ontrol lo g i c 1 6 bank 1 bank 2 bank 3 14 7 3 3 refresh c ounter 8 6 4 6 4 6 4 dq s , dq s # c olumns 0, 1, an d 2 c olumns 0, 1, an d 2 zq c l, zq cs to odt/output d rivers read d rivers dq[7:0] read fifo an d d ata mux data 8 3 bank 1 bank 2 bank 3 dm/tdq s (share d pin) tdq s # c k, c k# dq s , dq s # zq c al zq rzq c k, c k# ra s # we# c a s # cs # odt c ke re s et# c k, c k# dll dq[7:0] dq8 (1 . . . 8) (1, 2) sw1 sw2 v dd q/2 r tt _ nom r tt _ wr sw1 sw2 v dd q/2 r tt _ nom r tt _ wr sw1 sw2 v dd q/2 r tt _ nom r tt _ wr b c 4 ( b urst c hop) b c 4 b c 4 write d rivers an d input lo g i c data interfa c e c olumn 2 (sele c t upper or lower ni bb le for b c 4) (128 x 6 4) odt c ontrol v ss q a12 otf otf bank 5 bank 6 bank 7 bank 4 bank 7 bank 4 bank 5 bank 6 13 row- a dd ress mux c ontrol lo g i c c olumn- a dd ress c ounter/ lat c h mo d e re g isters 10 c omman d d e c o d e a[12:0] ba[2:0] 13 a dd ress re g ister 1 6 (128 x128) 1 6 ,384 i/o g atin g dm mask lo g i c c olumn d e c o d er bank 0 memory array (8192 x 128 x 128) bank 0 row- a dd ress lat c h an d d e c o d er 8,192 s ense amplifiers bank c ontrol lo g i c 1 6 bank 1 bank 2 bank 3 13 7 3 3 refresh c ounter 1 6 128 128 128 ldq s , ldq s #, udq s , udq s # c olumn 0, 1, an d 2 c olumns 0, 1, an d 2 zq c l, zq cs to odt/output d rivers b c 4 read d rivers dq[15:0] read fifo an d d ata mux data 1 6 b c 4 ( b urst c hop) 3 bank 1 bank 2 bank 3 ldm/udm c k, c k# ldq s , ldq s # udq s , udq s # zq c al zq rzq odt c ke c k, c k# ra s # we# c a s # cs # re s et# c k, c k# dll dq[15:0] (1 . . . 1 6 ) (1 . . . 4) (1, 2) sw1 sw2 v dd q/2 r tt _ nom r tt _ wr b c 4 sw1 sw2 v dd q/2 r tt _ nom r tt _ wr sw1 sw2 v dd q/2 r tt _ nom r tt _ wr c olumn 2 (sele c t upper or lower ni bb le for b c 4) data interfa c e write d rivers an d input lo g i c odt c ontrol v ss q a12 otf otf
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_d2.fm - rev. d 8/1/08 en 14 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram ball assignments and descriptions ball assignments and descriptions figure 6: 78-ball fbga ? x4, x8 ball assignments (top view) notes: 1. ball descriptions listed in table 3 on page 17 are listed as ?x4, x8? if uni q ue; otherwise, x4 and x8 are the same. 2. a comma separates the configuration; a slash defines a selectable function. 3. example d7 = nf, nf/tdqs#. nf applies to th e x4 configuration only. nf/tdqs# applies to the x8 configuration only?selectable between nf or tdqs# via mrs (symbols are defined in table 3 on page 17). 1234 6 789 5 v ss v ss v dd q v ss q v ref dq n c odt n c v ss v dd v ss v dd v ss v dd v ss q dq2 nf, dq 6 v dd q v ss v dd cs # ba0 a3 a5 a7 re s et# n c dq0 dq s dq s # nf, dq4 ra s # c a s # we# ba2 a0 a2 a9 a13 nf, nf/tdq s # dm, dm/tdq s dq1 v dd nf, dq7 c k c k# a10/ap n c a12/b c # a1 a11 n c v dd v dd q v ss q v ss q v dd q n c c ke n c v ss v dd v ss v dd v ss v ss v ss q dq3 v ss nf, dq5 v ss v dd zq v ref c a ba1 a4 a 6 a8 a b c d e f g h j k l m n
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_d2.fm - rev. d 8/1/08 en 15 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram ball assignments and descriptions figure 7: 86-ball fbga ? x4, x8 ball assignments (top view) notes: 1. ball descriptions listed in table 4 on page 19 are listed as ?x4, x8? if uni q ue; otherwise, x4 and x8 are the same. 2. a comma separates the configuration; a slash defines a selectable function. 3. example d7 = nf, nf/tdqs#. nf applies to th e x4 configuration only. nf/tdqs# applies to the x8 configuration only?selectable between nf or tdqs# via mrs (symbols are defined in table 4 on page 19). 1234 6 789 5 n c v ss v ss v dd q v ss q v ref dq n c odt n c v ss v dd v ss v dd v ss n c v dd v ss q dq2 nf, dq 6 v dd q v ss v dd cs # ba0 a3 a5 a7 re s et# n c n c dq0 dq s dq s # nf, dq4 ra s # c a s # we# ba2 a0 a2 a9 a13 n c n c nf, nf/tdq s # dm, dm/tdq s dq1 v dd nf, dq7 c k c k# a10/ap n c a12/b c # a1 a11 n c n c n c v dd v dd q v ss q v ss q v dd q n c c ke n c v ss v dd v ss v dd v ss n c v ss v ss q dq3 v ss nf, dq5 v ss v dd zq v ref c a ba1 a4 a 6 a8 a b c d e f g h j k l m n p r t u v w
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_d2.fm - rev. d 8/1/08 en 16 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram ball assignments and descriptions figure 8: 96-ball fbga ? x16 ball assignments (top view) notes: 1. ball descriptions listed in table 5 on page 21 are listed as ?x4, x8? if uni q ue; otherwise, x4 and x8 are the same. 2. a comma separates the configuration; a slash defines a selectable function. 3. example d7 = nf, nf/tdqs#. nf applies to th e x4 configuration only. nf/tdqs# applies to the x8 configuration only?selectable between nf or tdqs# via mrs (symbols are defined in table 5 on page 21). 1234 6 789 5 a b c d e f g h j k l m n p r t v dd q v ss q v dd q v ss q v ss v dd q v ss q v ref dq n c odt n c v ss v dd v ss v dd v ss dq13 v dd dq11 v dd q v ss q dq2 dq 6 v dd q v ss v dd cs # ba0 a3 a5 a7 re s et# dq15 v ss dq9 udm dq0 ldq s ldq s # dq4 ra s # c a s # we# ba2 a0 a2 a9 n c dq12 udq s # udq s dq8 ldm dq1 v dd dq7 c k c k# a10/ap n c a12/b c # a1 a11 n c v dd q dq14 dq10 v ss q v ss q dq3 v ss dq5 v ss v dd zq v ref c a ba1 a4 a 6 a8 v ss v ss q v dd q v dd v dd q v ss q v ss q v dd q n c c ke n c v ss v dd v ss v dd v ss
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_d2.fm - rev. d 8/1/08 en 17 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram ball assignments and descriptions table 3: 78-ball fbga ? x4, x8 ball descriptions ball assignments symbol type description k3, l7, l3, k2, l8, l2, m8, m2, n8, m3, h7, m7, k7, n3 a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10/ap, a11, a12/bc#, a13 input address inputs: provide the row address for activate commands, and the column address and auto precharge bit (a10) for read/ write commands, to select one location out of the memory array in the respective bank. a10 sampled during a precharge command determines whether the precharge applies to one bank (a10 low, bank selected by ba[2:0]) or all banks (a10 high). the address inputs also provide the op-code during a load mode command. address inputs are referenced to v ref ca. a12/bc#: when enabled in the mode register (mr), a12 is sa mpled during read and write commands to determine whether bu rst chop (on-the-fly) will be performed (high = bl8 or no burst chop, low = bc4 burst chop). see table 62 on page 91. j2, k8, j3 ba0, ba1, ba2 input bank address inputs: ba[2:0] define the bank to which an activate, read, write, or precharge command is being applied. ba[2:0] define which mode register (mr0, mr1, mr2, or mr3) is loaded during the load mode comma nd. ba[2:0] are referenced to v ref ca. f7, g7 ck, ck# input clock: ck and ck# are differential clock inputs. all control and address input signals are sampled on the crossing of the positive edge of ck and the negative edge of ck#. output data strobe (dqs, dqs#) is referenced to th e crossings of ck and ck#. g9 cke input clock enable: cke enables (registered high) and disables (registered low) internal circui try and clocks on the dram. the specific circuitry that is enable d/disabled is dependent upon the ddr3 sdram configuration and operating mode. taking cke low provides precharge power-down and self refresh operations (all banks idle), or active power-down (row active in any bank). cke is synchronous for power-down entry and exit and for self refresh entry. cke is asynchronous for self refresh exit. input buffers (excluding ck, ck#, cke, reset# , and odt) are disabled during power-down. input buffers (excludi ng cke and reset#) are disabled during self refresh. cke is referenced to v ref ca. h2 cs# input chip select: cs# enables (registered low) and disables (registered high) the command decoder. all co mmands are masked when cs# is registered high. cs# provides for ex ternal rank selection on systems with multiple ranks. cs# is cons idered part of the command code. cs# is referenced to v ref ca. b7 dm input input data mask: dm is an input mask signal for write data. input data is masked when dm is samp led high along with the input data during a write access. although the dm ball is input-only, the dm loading is designed to match that of the dq and dqs balls. dm is referenced to v ref dq. dm has an optional use as tdqs on the x8. g1 odt input on-die termination: odt enables (registered high) and disables (registered low) termination re sistance internal to the ddr3 sdram. when enabled in normal oper ation, odt is only applied to each of the following balls: dq[7:0 ], dqs, dqs#, and dm for the x8; dq[3:0], dqs, dqs#, and dm for th e x4. the odt input is ignored if disabled via the load mode co mmand. odt is referenced to v ref ca. f3, g3, h3 ras#, cas#, we# input command inputs: ras#, cas#, and we# (along with cs#) define the command being entered and are referenced to v ref ca.
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_d2.fm - rev. d 8/1/08 en 18 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram ball assignments and descriptions n2 reset# input reset: reset# is an active low cmos input referenced to v ss . the reset# input receiver is a cmos inpu t defined as a rail-to-rail signal with dc high 0.8 v dd q and dc low 0.2 v dd q. reset# assertion and desertio n are asynchronous. b3, c7, c2, c8 dq0, dq1, dq2, dq3 i/o data input/output: bidirectional data bus fo r the x4 configuration. dq[3:0] are referenced to v ref dq. b3, c7, c2, c8, e3, e8, d2, e7 dq0, dq1, dq2, dq3, dq4, dq5, dq6, dq7 i/o data input/output: bidirectional data bus fo r the x8 configuration. dq[7:0] are referenced to v ref dq. c3, d3 dqs, dqs# i/o data strobe: output with read data. e dge-aligned with read data. input with write data. cent er-aligned to write data. b7, a7 tdqs, tdqs# output termination data strobe: applies to the x8 configuration only. when tdqs is enabled, dm is disabled, and the tdqs and tdqs# balls provide termination resistance. a2, a9, d7, g2, g8, k1, k9, m1, m9 v dd supply power supply: 1.5v 0.075v. b9, c1, e2, e9 v dd q supply dq power supply: 1.5v 0.075v. isolated on the device for improved noise immunity. j8 v ref ca supply reference voltage for control, command, and address: v ref ca must be maintained at all times (inc luding self refresh) for proper device operation. e1 v ref dq supply reference voltage for data: v ref dq must be maintained at all times (including self refresh) for proper device operation. a1, a8, b1, d8, f2, f8, j1, j9, l1, l9, n1, n9 v ss supply ground. b2, b8, c9, d1, d9 v ss q supply dq ground: isolated on the device for improved noise immunity. h8 zq reference external reference ball for output drive calibration: this ball is tied to an external 240 resistor (rzq), which is tied to v ss q. a3, j7, n7, f9, h1, f1, h9 nc ? no connect: these balls should be left unconnected (the ball has no connection to the dram or to other balls). a7, d2, e3, e7, e8 nf ? no function: when configured as a x4 device, these balls are nf. when configured as a x8 device, these balls are defined as tdqs#, dq[7:4]. table 3: 78-ball fbga ? x4, x8 ball descriptions (continued) ball assignments symbol type description
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_d2.fm - rev. d 8/1/08 en 19 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram ball assignments and descriptions table 4: 86-ball fbga ? x4, x8 ball descriptions ball assignments symbol type description n3, p7, p3, n2, p8, p2, r8, r2, t8, r3, l7, r7, n7, t3 a0, a1, a2, a3, a4, a5, a6, a7, a8, a9 a10/ap, a11, a12/bc#, a13 input address inputs: provide the row addre ss for activate commands, and the column address and auto precharge bit (a10) for read/ write commands, to select one loca tion out of the memory array in the respective bank. a10 samp led during a precharge command determines whether the precharge applies to one bank (a10 low, bank selected by ba[2:0 ]) or all banks (a10 high). the address inputs also provide the op-code during a load mode command. address inputs are referenced to v ref ca. a12/bc#: when enabled in the mode register (mr), a12 is sampled during read and write commands to determine whether bu rst chop (on-the- fly) will be performed (high = bl8 or no burst chop, low = bc4 burst chop). see table 62 on page 91. m2, n8, m3 ba0, ba1, ba2 input bank address inputs: ba[2:0] define the bank to which an activate, read, write, or precharge command is being applied. ba[2:0] define which mode register (mr0, mr1, mr2, or mr3) is loaded during the load mode comm and. ba[2:0] are referenced to v ref ca. j7, k7 ck, ck# input clock: ck and ck# are differential clock inputs. all control and address input signals are sampled on the crossing of the positive edge of ck and the negative edge of ck#. output data strobe (dqs, dqs#) is referenced to the crossings of ck and ck#. k9 cke input clock enable: cke enables (registere d high) and disables (registered low) internal circui try and clocks on the dram. the specific circuitry that is enable d/disabled is dependent upon the ddr3 sdram configuration and op erating mode. taking cke low provides precharge power-down an d self refresh operations (all banks idle), or active power-down (row active in any bank). cke is synchronous for power-down entry and exit and for self refresh entry. cke is asynchronous for self refresh exit. input buffers (excluding ck, ck#, cke, reset#, and odt) are disabled during power-down. input buffer s (excluding cke and reset#) are disabled during self refresh. cke is referenced to v ref ca. l2 cs# input chip select: cs# enables (registered low) and disables (registered high) the command decoder. all co mmands are masked when cs# is registered high. cs# provides for ex ternal rank selection on systems with multiple ranks. cs# is cons idered part of the command code. cs# is referenced to v ref ca. e7 dm input input data mask: dm is an input mask signal for write data. input data is masked when dm is samp led high along with the input data during a write access. although the dm ball is input-only, the dm loading is designed to match that of the dq and dqs balls. dm is referenced to v ref dq. dm has an optional use as tdqs on the x8. k1 odt input on-die termination: odt enables (registered high) and disables (registered low) termination re sistance internal to the ddr3 sdram. when enabled in normal op eration, odt is only applied to each of the following balls: dq[7:0 ], dqs, dqs#, and dm for the x8; dq[3:0], dqs, dqs#, and dm for th e x4. the odt input is ignored if disabled via the load mode co mmand. odt is referenced to v ref ca. j3, k3, l3 ras#, cas#, we# input command inputs: ras#, cas#, and we# (along with cs#) define the command being entered and are referenced to v ref ca.
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_d2.fm - rev. d 8/1/08 en 20 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram ball assignments and descriptions t2 reset# input reset: reset# is an active low cmos input referenced to v ss . the reset# input receiver is a cmos input defined as a rail-to-rail signal with dc high 0.8 v dd q and dc low 0.2 v dd q. reset# assertion and desertion are asynchronous. e3, f7, f2, f8 dq0, dq1, dq2, dq3 i/o data input/output: bidirectional data bus fo r the x4 configuration. dq[3:0] are referenced to v ref dq. e3, f7, f2, f8, h3, h8, g2, h7 dq0, dq1, dq2, dq3, dq4, dq5, dq6, dq7 i/o data input/output: bidirectional data bus fo r the x8 configuration. dq[7:0] are referenced to v ref dq. f3, g3 dqs, dqs# i/o data strobe: output with read data. edge -aligned with read data. input with write data. center-aligned to write data. e7, d7 tdqs, tdqs# output termination data strobe: applies to the x8 configuration only. when tdqs is enabled, dm is disabled, and the tdqs and tdqs# balls provide termination resistance. d2, d9, g7, k2, k8, n1, n9, r1, r9 v dd supply power supply: 1.5v 0.075v. e9, f1, h2, h9 v dd q supply dq power supply: 1.5v 0.075v. isolated on the device for improved noise immunity. m8 v ref ca supply reference voltage for control, command, and address: v ref ca must be maintained at all times (i ncluding self refresh) for proper device operation. h1 v ref dq supply reference voltage for data: v ref dq must be maintained at all times (including self refresh) for proper device operation. d1, d8, e1, g8, j2, j8, m1, m9, p1, p9, t1, t9 v ss supply ground. e2, e8, f9, g1, g9 v ss q supply dq ground: isolated on the device fo r improved noise immunity. l8 zq reference external reference ball for output drive calibration: this ball is tied to an external 240 resistor (rzq), wh ich is tied to v ss q. a1, a3, a7, a9, d3, j1, j9, l1, l9, m7, t7, w1, w3, w7, w9 nc ? no connect: these balls should be left unconnected (the ball has no connection to the dram or to other balls). d7, g2, h3, h7, h8 nf ? no function: when configured as a x4 device, these balls are nf. when configured as a x8 device, these balls are defined as tdqs#, dq[7:4]. table 4: 86-ball fbga ? x4, x8 ball descriptions (continued) ball assignments symbol type description
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_d2.fm - rev. d 8/1/08 en 21 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram ball assignments and descriptions table 5: 96-ball fbga ? x16 ball descriptions ball assignments symbol type description n3, p7, p3, n2, p8, p2, r8, r2, t8, r3, l7, r7, n7 a0, a1, a2, a3, a4, a5, a6, a7, a8, a9 a10/ap, a11, a12/bc# input address inputs: provide the row address for activate commands, and the column address and auto precharge bit (a10) for read/ write commands, to select one loca tion out of the memory array in the respective bank. a10 sample d during a precharge command determines whether the precharge ap plies to one bank (a10 low, bank selected by ba[2 :0]) or all banks (a10 high). the address inputs also provide the op-code during a load mode command. address inputs are referenced to v ref ca. a12/bc#: when enabled in the mode register (mr), a12 is sampled during read and write commands to determine whether burs t chop (on-the- fly) will be performed (high = bl8 or no burst chop, low = bc4 burst chop). see table 62 on page 91. m2, n8, m3 ba0, ba1, ba2 input bank address inputs: ba[2:0] define the bank to which an activate, read, write, or precharge command is being applied. ba[2:0] define which mode register (mr0, mr1, mr2, or mr3) is loaded during the load mode comm and. ba[2:0] are referenced to v ref ca. j7, k7 ck, ck# input clock: ck and ck# are differential clock inputs. all control and address input signals are sampled on the crossing of the positive edge of ck and the negative edge of ck#. output data strobe (dqs, dqs#) is referenced to the crossings of ck and ck#. k9 cke input clock enable: cke enables (registere d high) and disables (registered low) internal circui try and clocks on the dram. the specific circuitry that is enabled/disabled is dependent upon the ddr3 sdram configuration and op erating mode. taking cke low provides precharge power-down an d self refresh operations (all banks idle),or active power-down (r ow active in any bank). cke is synchronous for power-down entry and exit and for self refresh entry. cke is asynchronous for self refresh exit. input buffers (excluding ck, ck#, cke, reset#, and odt) are disabled during power-down. input buffers (excluding cke and reset#) are disabled during self refresh. cke is referenced to v ref ca. l2 cs# input chip select: cs# enables (registered low) and disables (registered high) the command decoder. all co mmands are masked when cs# is registered high. cs# provides for ex ternal rank selection on systems with multiple ranks. cs# is cons idered part of the command code. cs# is referenced to v ref ca. e7 ldm input input data mask: ldm is a lower-byte, input mask signal for write data. lower-byte input data is masked when ldm is sampled high along with the input data during a write access. although the ldm ball is input-only, the ldm loading is designed to match that of the dq and dqs balls. ldm is referenced to v ref dq. k1 odt input on-die termination: odt enables (registered high) and disables (registered low) termination re sistance internal to the ddr3 sdram. when enabled in normal operation, odt is only applied to each of the following balls: dq[15:0], ldqs, ldqs#, udqs, udqs#, ldm, and udm for the x16; dq0[7: 0], dqs, dqs#, dm/tdqs, and nf/ tdqs# (when tdqs is enabled) for the x8; dq[3:0], dqs, dqs#, and dm for the x4. the odt input is ignored if disabl ed via the load mode command. odt is referenced to v ref ca. j3, k3, l3 ras#, cas#, we# input command inputs: ras#, cas#, and we# (along with cs#) define the command being entered and are referenced to v ref ca.
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_d2.fm - rev. d 8/1/08 en 22 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram ball assignments and descriptions t2 reset# input reset: reset# is an active low cmos input referenced to v ss . the reset# input receiver is a cmos input defined as a rail-to-rail signal with dc high 0.8 v dd q and dc low 0.2 v dd q. reset# assertion and desertion are asynchronous. d3 udm input input data mask: udm is an upper-byte, input mask signal for write data. upper-byte input data is masked when udm is sampled high along with that input data during a write access. although the udm ball is input-only, the udm loading is designed to match that of the dq and dqs ball s. udm is referenced to v ref dq. e3, f7, f2, f8, h3, h8, g2, h7 dq0, dq1, dq2, dq3, dq4, dq5, dq6, dq7 i/o data input/output: lower byte of bidirectional data bus for the x16 configuration. dq[7:0] are referenced to v ref dq. d7, c3, c8, c2, a7, a2, b8, a3 dq8, dq9, dq10, dq11, dq12, dq13, dq14, dq15 i/o data input/output: upper byte of bidirectional data bus for the x16 configuration. dq[15:8] are referenced to v ref dq. f3, g3 ldqs, ldqs# i/o lower byte data strobe: output with read data. edge-aligned with read data. input with write data. center-aligned to write data. c7, b7 udqs, udqs# i/o upper byte data strobe: output with read data. edge-aligned with read data. input with write data. dqs is center-aligned to write data. b2, d9, g7, k2, k8, n1, n9, r1, r9 v dd supply power supply: 1.5v 0.075v. a1, a8, c1, c9, d2, e9, f1, h2, h9 v dd q supply dq power supply: 1.5v 0.075v. isolated on the device for improved noise immunity. m8 v ref ca supply reference voltage for control, command, and address: v ref ca must be maintained at all times (i ncluding self re fresh) for proper device operation. h1 v ref dq supply reference voltage for data: v ref dq must be maintained at all times (including self refresh) for proper device operation. a9, b3, e1, g8, j2, j8, m1, m9, p1, p9, t1, t9 v ss supply ground. b1, b9, d1, d8, e2, e8, f9, g1, g9 v ss q supply dq ground: isolated on the device fo r improved noise immunity. l8 zq reference external reference ball for output drive calibration: this ball is tied to an external 240 resistor (rzq), wh ich is tied to v ss q. j1, j9, l1, l9, m7, t3, t7 nc ? no connect: these balls should be left unconnected (the ball has no connection to the dram or to other balls). table 5: 96-ball fbga ? x16 ball descriptions (continued) ball assignments symbol type description
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_d2.fm - rev. d 8/1/08 en 23 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram package dimensions package dimensions figure 9: 78-ball fbga ? x4, x8; ?jp? notes: 1. all dimensions are in millimeters. ball a1 id 1.2 max 0.8 typ 0.8 0.1 seating plane a 9.6 ctr 6.4 ctr 0.12 a 78x ?0.45 11.5 0.15 ball a1 id 0.8 typ 8 0.15 0.25 min 9 8 7 3 2 1 a b c d e f g h j k l m n dimensions apply to solder balls post- reflow on ?0.33 nsmd ball pads.
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_d2.fm - rev. d 8/1/08 en 24 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram package dimensions figure 10: 78-ball fbga ? x4, x8; ?hx? notes: 1. all dimensions are in millimeters. ball a1 id seating plane 0.12 a a 0.8 0.1 1.2 max 0.25 min 9 0.15 ball a1 id 9.6 ctr solder ball material: sac305. dimensions apply to solder balls post- reflow on ?0.33 nsmd ball pads. 78x ?0.45 11.5 0.15 0.8 typ 0.8 typ 6.4 ctr 9 8 7 3 2 1 a b c d e f g h j k l m n
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_d2.fm - rev. d 8/1/08 en 25 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram package dimensions figure 11: 86-ball fbga ? x4, x8 notes: 1. all dimensions are in millimeters. ball a1 id s eatin g plane 0.8 0.1 dimensions apply to sol d er b alls post-reflow on ?0.33 n s md b all pa d s. 0.12 a a 15.5 0.15 2.4 typ 14.4 c tr ball a1 id 8 6 x ?0.45 1.2 max 0.25 min 9 0.15 0.8 typ 0.8 typ 6 .4 c tr 9 8 7 3 2 1 a d e f g h j k l m n p r t w
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_d2.fm - rev. d 8/1/08 en 26 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram package dimensions figure 12: 96-ball fbga ? x16 notes: 1. all dimensions are in millimeters. ball a1 id s eatin g plane 0.8 0.1 s ol d er b all material: s a c 305. dimensions apply to sol d er b alls post-reflow on ?0.33 n s md b all pa d s. 0.12 a a 15.5 0.15 0.8 typ 1.2 max 12 c tr ball a1 id 0.8 typ 9 0.15 0.25 min 6 .4 c tr 9 6 x ?0.45 9 8 7 3 2 1 a b c d e f g h j k l m n p r s
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_d2.fm - rev. d 8/1/08 en 27 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram electrical specifications electrical specifications absolute ratings stresses greater than those listed in table 6 may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. notes: 1. v dd and v dd q must be within 300mv of each other at all times, and v ref must not be greater than 0.6 v dd q. when v dd and v dd q are less than 500mv, v ref may be 300mv. 2. max operating case temperature. t c is measured in the center of the package (see figure 13 on page 28). 3. device functionality is no t guaranteed if the dram de vice exceeds the maximum t c during operation. input/output capacitance notes: 1. v dd = +1.5v 0.075mv, v dd q = v dd , v ref = v ss , f = 100 mhz, t c = 25c. v out ( dc )=0.5v dd q, v out (peak-to-peak) = 0.1v. 2. dm input is grouped with i/o pins, reflecting the fact that they are matched in loading. 3. includes tdqs, tdqs#. c ddqs is for dqs vs. dqs# and tdqs vs. tdqs# separately. 4. c dio = c io (dq) - 0.5 (c io [dqs] + c io [dqs#]). 5. excludes ck, ck#; ctrl = odt, cs#, and cke; cmd = ras#, cas#, and we#; addr = a[ n :0], ba[2:0]. 6. c di _ ctrl = c i (ctrl) - 0.5 (c ck [ck] + c ck [ck#]). 7. c di _ cmd _ addr = c i (cmd_addr) - 0.5 (c ck [ck] + c ck [ck#]). table 6: absolute maximum ratings symbol parameter min max units notes v dd v dd supply voltage relative to v ss ?0.4 1.975 v 1 v dd qv dd supply voltage relative to v ss q?0.4 1.975 v v in , v out voltage on any pin relative to v ss ?0.4 1.975 v t c operating case temperature 0 95 c 2, 3 t stg storage temperature ?55 150 c table 7: input/output capacitance note 1 applies to the entire table capacitance parameters symbol ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 units notes min max min max min max min max ck and ck# c ck 0.8 1.6 0.8 1.6 0.8 1.4 0.8 1.4 pf c: ck to ck# c dck 00.1500.1500.1500.15pf single-end i/o: dq, dm c io 1.5 3.0 1.5 3.0 1.5 2.5 1.5 2.3 pf 2 differential i/o: dqs, dqs#, tdqs, tdqs# c io 1.5 3.0 1.5 3.0 1.5 2.5 1.5 2.3 pf 3 c: dqs to dqs#, tdqs, tdqs# c ddqs 0 0.2 0 0.2 00.1500.15pf 3 c: dq to dqs c dio ?0.50.3?0.50.3?0.50.3?0.50.3 pf 4 inputs (ctrl, cmd, addr) c i 0.75 1.5 0.75 1.5 0.75 1.3 0.75 1.3 pf 5 c: ctrl to ck c di _ ctrl ?0.50.3?0.50.3?0.40.2?0.40.2 pf 6 c: cmd_addr to ck c di _ cmd _ addr ?0.50.5?0.50.5?0.40.4?0.40.4 pf 7
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_d2.fm - rev. d 8/1/08 en 28 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram thermal characteristics thermal characteristics notes: 1. max operating case temperature. t c is measured in the center of the package (see figure 13 ). 2. a thermal solution must be desi gned to ensure the dram devi ce does not exceed the maxi- mum t c during operation. 3. device functionality is not guaranteed if the dram device exceeds the maximum t c during operation. 4. if t c exceeds 85c, the dram must be refreshed externally at 2x refresh, which is a 3.9s interval refresh rate. the use of srt or asr (if available) must be enabled. 5. the thermal resistance data is based off of a number of samples from multiple lots and should be viewed as a typical number. figure 13: thermal measurement point table 8: thermal characteristics parameter/condition symbol value units notes operating case temperature t c 0 to 85 c 1, 2, 3 t c 0 to 95 c 1, 2, 3, 4 junction-to-case (top) 78-ball jc 3.2 c/w 5 86-ball 2.8 96-ball 2.8 (l/2) l w (w/2) t c test point
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_d2.fm - rev. d 8/1/08 en 29 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram electrical specifications ? i dd specifications and conditions electrical specifications ? i dd specifications and conditions the following definitions are used within the i dd measurement tables: ?low: v in v il ( ac ) max; high: v in v ih ( ac ) min ? stable: inputs are stable at a high or low level ? floating: inputs are v ref =v dd q/2 ? switching: see tables 10 and 11 ta bl e 9 : i dd measurement conditions reference table number measurement conditions table 13 on page 31 i dd 0 and i dd 1 table 14 on page 33 i dd 2ps, i dd 2pf, i dd 2q, i dd 2n, i dd 3p, and i dd 3n table 15 on page 35 i dd 4r, i dd 4w table 16 on page 37 i dd 5b, i dd 6, i dd 6et table 17 on page 38 i dd 7 (see table 18 on page 38) table 10: definition of switching fo r command and address input signals switching for address (row/column) and comm and signals (cs#, ras#, cas#, and/or we#) address (row/column) if not otherwise stated, inputs are stab le at high or low during 4 clocks and then change to the opposite value (ax ax ax ax ax ax ax ax ax ax ax ax . . . ) bank address if not otherwise stated, the bank addresses should be swit ched in a similar fashion as the row/column addresses command (cs#, ras#, cas#, we#) define command background pattern = d d d d d d d d d d d d . . . where: d = (cs#, ras#, cas#, we#) = (high, low, low, low) d = (cs#, ras#, cas#, we#) = (high, high, high, high) if other commands are necessary (activate for i dd 0 or read for i dd 4r), the background pattern command is substituted by the respecti ve cs#, ras#, cas#, a nd we# levels of the necessary command table 11: definition of switching for data pins switching for data pins (dq, dqs, dm) data strobe (dqs) data strobe is changing be tween high and low after every clock cycle data (dq) data dq is changing between high and low every other da ta transfer (once per clock) for dq signals, which means that data dq is stable during one clock data masking (dm) no switching; dm must always be driven low
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_d2.fm - rev. d 8/1/08 en 30 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram electrical specifications ? i dd specifications and conditions notes: 1. i dd specifications are tested after th e device is properly initialized. 2. input slew rate is specified by ac parametric test conditions. 3. i dd parameters are specified with odt and th e output buffer is disabled (mr1[12]). 4. optional asr is disabl ed unless stated otherwise. table 12: timing parameters i dd parameter ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 units -25e -25 -187e -187 -15f -15e -15 -125f -125e -125 5-5-5 6-6-6 7-7-7 8-8-8 8-8-8 9-9-9 10-10-10 9-9-9 10-10-10 11-11-11 t ck (min) i dd 2.5 1.875 1.5 1.25 ns cl i dd 567889 10 9 10 11ck t rcd (min) i dd 12.5 15 13.13 15 12 13.5 15 11.25 12.5 13.75 ns t rc (min) i dd 50 52.5 50.63 52.50 48 49.5 51 46.25 47.5 48.75 ns t ras (min) i dd 37.5 37.5 37.5 37.5 36 36 36 35 35 35 ns t rp (min) 12.5 15 13.13 15 12 13.5 15 11.25 12.5 13.75 ns t faw x4, x8 40 40 37.5 37.5 30 30 30 30 30 30 ns x16 505050504545 45 40 40 40 ns t rrd i dd x4, x8 10 10 7.5 7.5 6 6 6 6 6 6 ns x16 101010107.57.5 7.5 7.5 7.5 7.5 ns t rfc 110 110 110 110 110 110 110 110 110 110 ns
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_d2.fm - rev. d 8/1/08 en 31 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram electrical specifications ? i dd specifications and conditions notes: 1. for further definition of input switching, see table 10 on page 29. 2. for further definition of data switching, see table 11 on page 29. table 13: i dd measurement conditions for i dd 0 and i dd 1 i dd test i dd 0: operating current 0 one bank activate to precharge i dd 1: operating current 1 one bank activate to read to precharge notes timing example ? figure 14 on page 32 cke high high external clock on on t ck t ck (min) i dd t ck (min) i dd t rc t rc (min) i dd t rc (min) i dd t ras t ras (min) i dd t ras (min) i dd t rcd n/a t rcd (min) i dd t rrd n/a n/a t rc n/a n/a cl n/a cl i dd al n/a 0 cs# high between activate and prechar ge high between activate, read, and precharge command inputs switching?the only exceptions are activate and precharge commands; example of -25e i dd 0 pattern: a0ddd dddd dddd ddd p0 switching?the only exceptions are activate and precharge commands; example of -25e i dd 1 pattern: a0ddd dr0dd dddd ddd p0 1 row/column addresses row addresses switching; address input a10 must be low at all times row addresses switching; address input a10 must be low at all times 1 bank addresses bank address is fixed (bank 0 ) bank address is fixed (bank 0 ) data i/o switching r ead data: output data switches after every clock cycle, which means that read data is stable during falling dqs; i/o should be floating when no read data 2 output buffer dq, dqs off off odt disabled disabled burst length n/a 8 fixed (via mr0) active banks bank 0 ; activate-to-precharge loop bank 0 ; activate-to-read-to-precharge loop idle banks all other all other special notes n/a n/a
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_d2.fm - rev. d 8/1/08 en 32 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram electrical specifications ? i dd specifications and conditions figure 14: i dd 1 example ? ddr3-800, 5-5-5, x8 (-25e) notes: 1. data dq is shown, but the output buffer should be switched off (per mr1[12] = 1) to achieve i out = 0ma (mr1[12] = 0 is reflected in this example; however, test conditions are mr1[12] = 1). address inputs are split into three parts. a[9:0] c k ba[2:0] a10 a[12:11] cs # ra s # c a s # we# c omman d i dd 1 measurement loop dq dm 0 3ff 000 3ff 000 3ff 0 30 30 d d# d# d rd d# d# d d d# d# d d d# pre d d d# d# 0011001 t0 t1 t2 t3 t4 t5 t 6 t7 t8 t9 t10 t12 t14 t1 6 t18 000 a c t t11 t13 t15 t17 1
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_d2.fm - rev. d 8/1/08 en 33 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram electrical specifications ? i dd specifications and conditions notes: 1. mr0[12] defines dll on/off behavior during precharge power-down only; dll on (fast exit, mr0[12] = 1) and dll off (slow exit, mr0[12] = 0). 2. for further definition of input switching, see table 10 on page 29. 3. for further definition of data switching, see table 11 on page 29. table 14: i dd measurement conditions for power-down currents name i dd 2ps precharge power-down current (slow exit) 1 i dd 2pf precharge power-down current (fast exit) 1 i dd 2q precharge quiet standby current i dd 2n precharge standby current i dd 3p active power-down current i dd 3n active standby current notes timing example n/a n/a n/a figure 15 on page 34 n/a figure 15 on page 34 cke low low high high low high external clockonononononon t ck t ck (min) i dd t ck(min) i dd t ck(min) i dd t ck (min) i dd t ck (min) i dd t ck (min) i dd t rc n/a n/a n/a n/a n/a n/a t ras n/a n/a n/a n/a n/a n/a t rcd n/a n/a n/a n/a n/a n/a t rrd n/a n/a n/a n/a n/a n/a t rc n/a n/a n/a n/a n/a n/a cl n/a n/a n/a n/a n/a n/a al n/a n/a n/a n/a n/a n/a cs# stable stable high high stable high command inputs stable stable stab le switching stable switching 2 row/column addresses stable stable stable swit ching stable switching 2 bank addresses stable stable sta ble switching stable switching 2 data i/o floating floating floating switching floating switching 3 output buffer dq, dqs off off off off off off odt disabled disabled disabled disabled disabled disabled burst length n/a n/a n/a n/a n/a n/a active banks none none none none all all idle banks all all all all none none special notes n/a n/a n/a n/a n/a n/a
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_d2.fm - rev. d 8/1/08 en 34 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram electrical specifications ? i dd specifications and conditions figure 15: i dd 2n/i dd 3n example ? ddr3-800, 5-5-5, x8 (-25e) c k ba[2:0] a[12:0] cs # ra s # c a s # we# dm 0 70 0000 1fff 0000 t0 t1 t2 t3 t4 t5 t 6 t7 t8 t9 t10 i dd 2n/i dd 3n measurement loop dq[7:0] ff 00 00 ff ff 00 ff ff 00 00 ff ff 00 00 ff ff 00 00 ff 00 00 ff c omman d d# d# d# d d# d# d# dd dd
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_d2.fm - rev. d 8/1/08 en 35 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram electrical specifications ? i dd specifications and conditions notes: 1. for further definition of input switching, see table 10 on page 29. 2. for further definition of data switching, see table 11 on page 29. table 15: i dd measurement conditions for i dd 4r, i dd 4w i dd test i dd 4r: burst read operating current i dd 4w: burst write operating current notes timing diagram example figure 16 on page 36 ? cke high high external clock on on t ck t ck (min) i dd t ck (min) i dd t rc n/a n/a t ras n/a n/a t rcd n/a n/a t rrd n/a n/a t rc n/a n/a cl cl i dd cl i dd al 0 0 cs# high between valid commands high between valid commands command inputs switching; read command/pattern: r0ddd r1ddd r2ddd r3ddd r4 . . . r x = read from bank x switching; write command/pattern: w0ddd w1ddd w2ddd w3ddd w4 . . . w x = write to bank x 1 row/column addresses column addresses switching; address input a10 must always be low column addresses switching; address input a10 must always be low 1 bank addresses bank address looping (0-to-1-to-2-to-3 . . . ) bank addre ss looping (0-to-1-to-2-to-3 . . . ) data i/o seamless read data burst (bl8): output data switches after every clock cycle, which means that read data is stable during falling dqs seamless write data burst (bl8): input data switches after every clock cycle, which means that write data is stable during falling dqs 2 output buffer dq, dqs off off odt disabled disabled burst length 8 fixed (via mr0) 8 fixed (via mr0) active banks all all idle banks none none special notes n/a dm always low
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_d2.fm - rev. d 8/1/08 en 36 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram electrical specifications ? i dd specifications and conditions figure 16: i dd 4r example ? ddr3-800, 5-5-5, x8 notes: 1. data dq is shown, but the output buffer should be switched off (per mr1[12] = 1) to achieve i out = 0ma (mr1[12] = 0 is reflected in this example; however, test conditions are mr1[12] = 1). address inputs are split into three parts. c k ba[2:0] a[9:0] a10 a[12:11] cs # ra s # c a s # we# c md[2:0] dq[7:0] dm 01 3 000 3ff 3ff 03 03 rd d d# d# rd d d# d# d d# d# rd d 00 00 ff ff 00 00 ff ff 00 00 ff ff 00 00 ff ff t0 t1 t2 t3 t4 t5 t 6 t7 t8 t9 t10 t11 t12 rd s tart measurement loop 2 000
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_d2.fm - rev. d 8/1/08 en 37 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram electrical specifications ? i dd specifications and conditions notes: 1. for further definition of input switching, see table 10 on page 29. 2. for further definition of data switching, see table 11 on page 29. table 16: i dd measurement conditions for i dd 5b, i dd 6, i dd 6et i dd test i dd 5b: refresh current i dd 6: self refresh current normal temperature range t c = 0c to 85c i dd 6et: self refresh current extended temperature range t c = 0c to 95c notes cke high low low external clock on off, ck and ck# = low off, ck and ck# = low t ck t ck (min) i dd n/a n/a t rc n/a n/a n/a t ras n/a n/a n/a t rcd n/a n/a n/a t rrd n/a n/a n/a t rc t rfc (min) i dd n/a n/a cl n/a n/a n/a al n/a n/a n/a cs# high between valid commands floating floating command inputs switching floating floating 1 row/column addresses switching floating floating 1 bank addresses switching floating floating 1 data i/o switching floating floating 2 output buffer dq, dqs disabled disabled disabled odt disabled disabled disabled burst length n/a n/a n/a active banks refresh command every t rfc (min) n/a n/a idle banks none n/a n/a special notes n/a srt disabled srt enabled
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_d2.fm - rev. d 8/1/08 en 38 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram electrical specifications ? i dd specifications and conditions notes: 1. a0 = activate bank 0 ; ra0 = read with auto precharge bank 0 ; d = deselect. table 17: i dd measurement conditions for i dd 7 i dd test i dd 7: all banks interleaved read current cke high external clock on t ck t ck (min) i dd t rc t rc (min) i dd t ras t ras (min) i dd t rcd t rcd (min) i dd t rrd t rrd (min) i dd t rc n/a cl cl i dd al cl - 1 cs# high between valid commands command inputs see table 10 on page 29 for patterns row/column addresses stable during deselects (des) bank addresses looping (see tabl e 10 on page 29 for patterns) data i/o read data (bl8): output data switches afte r every clock cycle, which means that read data is stable during falling dqs; i/o should be fl oating when no read data is being driven output buffer dq, dqs off odt disabled burst length 8 fixed (via mr0) active banks all, rotational idle banks n/a table 18: i dd 7 patterns speed bin width i dd 7 pattern ddr3-800 (-25, -25e) x4, x8 a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d a4 ra4 d d a5 ra5 d d a6 ra6 d d a7 ra7 d d a0 . . . x16 a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d d a4 ra4 d d a5 ra5 d d a6 ra6 d d a7 ra7 d d d d d d a0 . . . ddr3-1066 (-187, -187e) x4, x8 a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d d a4 ra4 d d a5 ra5 d d a6 ra6 d d a7 ra7 d d d d d d a0 . . . x16 a0 ra0 d d d d a1 ra1 d d d d a2 ra2 d d d d a3 ra3 d d d d d d d a4 ra4 d d d d a5 ra5 d d d d a6 ra6 d d d d a7 ra7 d d d d d d d a0 . . . ddr3-1333 (-15, -15e, -15f) x4, x8 a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d d a4 ra4 d d a5 ra5 d d a6 ra6 d d a7 ra7 d d d d d d a0 . . . x16 a0 ra0 d d d a1 ra1 d d d a2 ra2 d d d a3 ra3 d d d d d d d d d d d d d a4 ra4 d d d a5 ra5 d d d a6 ra6 d d d a7 ra7 d d d d d d d d d d d d d a0 . . . ddr3-1600 (-125e, -125f, -125) x4, x8 a0 ra0 d d d a1 ra1 d d d a2 ra2 d d d a3 ra3 d d d d d d d a4 ra4 d d d a5 ra5 d d d a6 ra6 d d d a7 ra7 d d d d d d d a0 . . . x16 a0 ra0 d d d d a1 ra1 d d d d a2 ra2 d d d d a3 ra3 d d d d d d d d d d d d a4 ra4 d d d d a5 ra5 d d d d a6 ra6 d d d d a7 ra7 d d d d d d d d d d d d a0 . . .
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_d2.fm - rev. d 8/1/08 en 39 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram electrical characteristics ? i dd specifications electrical characteristics ? i dd specifications i dd values are for full operating range of voltage and temperature unless otherwise noted. notes: 1. t c = 85c; srt and asr are disabled. 2. enabling asr could increase i dd x by up to an additional 2ma. 3. restricted to t c (max) = 85c. 4. t c = 85c; asr and odt are disabled; srt is enabled. table 19: i dd maximum limits speed bin ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 units notes i dd width i dd 0 x4 65 75 85 95 ma 1, 2 x8 90 100 110 120 ma 1, 2 x16 90 100 110 120 ma 1, 2 i dd 1 x4 85 95 105 115 ma 1, 2 x8 110 120 130 140 ma 1, 2 x16 110 130 150 170 ma 1, 2 i dd 2pslow (s)10101010ma1, 2 fast (f)25252525ma1, 2 i dd 2q all 40 45 50 55 ma 1, 2 i dd 2nall45505560ma1, 2 i dd 3p all 25 30 35 40 ma 1, 2 i dd 3n x4, x8 50 55 60 65 ma 1, 2 x1650556065ma1, 2 i dd 4r x4 130 160 200 250 ma 1, 2 x8 130 160 200 250 ma 1, 2 x16 190 230 270 315 ma 1, 2 i dd 4w x4 130 160 190 225 ma 1, 2 x8 130 160 190 225 ma 1, 2 x16 210 265 325 400 ma 1, 2 i dd 5b all 200 220 240 260 ma 1, 2 i dd 6all6666ma1, 2, 3 i dd 6et all 9 9 9 9 ma 2, 4 i dd 7 x4 230 250 315 400 ma 1, 2 x8 350 390 490 600 ma 1, 2 x16 350 380 420 460 ma 1, 2
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_3.fm - rev. d 8/1/08 en 40 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram electrical specifications ? dc and ac electrical specific ations ? dc and ac dc operating conditions notes: 1. v dd and v dd q must track one another. v dd q must be less than or e q ual to v dd . v ss = v ss q. 2. v dd and v dd q may include ac noise of 50mv (250 kh z to 20 mhz) in addition to the dc (0hz to 250 khz) specifications. v dd and v dd q must be at same level for valid ac timing parameters. 3. v ref (see table 21). 4. the minimum limit re q uirement is for testing purposes. the leakage current on the v ref pin should be minimal. input operating conditions notes: 1. v ref ca( dc ) is expected to be approximately 0.5 v dd and to track variations in the dc level. externally generated pe ak noise (noncommon mode) on v ref ca may not exceed 1 percent v dd around the v ref ca( dc ) value. peak-to-peak ac noise on v ref ca should not exceed 2 percent of v ref ca( dc ). 2. dc values are determined to be less than 20 mhz in fre q uency. dram must meet specifica- tions if the dram induce s additional ac noise gr eater than 20 mhz in fre q uency. 3. v ref dq( dc ) is expected to be approximately 0.5 v dd and to track variations in the dc level. externally generated pe ak noise (noncommon mode) on v ref dq may not exceed 1 percent v dd around the v ref dq( dc ) value. peak-to-peak ac noise on v ref dq should not exceed 2 percent of v ref dq( dc ). 4. v tt is not applied direct ly to the device. v tt is a system supply for signal termination resis- tors. min and max values are system-dependent. table 20: dc electrical characteristics and operating conditions all voltages are referenced to v ss parameter/condition symbol min nom max units notes supply voltage v dd 1.425 1.5 1.575 v 1, 2 i/o supply voltage v dd q 1.425 1.5 1.575 v 1, 2 input leakage current any input 0v v in v dd , v ref pin 0v v in 1.1v (all other pins not under test = 0v) i i ?2 ? 2 a v ref supply leakage current v ref dq = v dd /2 or v ref ca = v dd /2 (all other pins not under test = 0v) i vref ?1 ? 1 a 3, 4 table 21: dc electrical charact eristics and input conditions all voltages are referenced to v ss parameter/condition symbol min nom max units notes input reference voltage command/address bus v ref ca( dc )0.49v dd 0.5 v dd 0.51 v dd v1, 2 i/o reference voltage dq bus v ref dq( dc )0.49v dd 0.5 v dd 0.51 v dd v2, 3 command/address termination voltage (system level, not direct dram input) v tt ?0.5v dd q? v4
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_3.fm - rev. d 8/1/08 en 41 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram electrical specifications ? dc and ac notes: 1. all voltages are referenced to v ref . v ref is v ref ca for control, comma nd, and address. all slew rates and setup/hold times ar e specified at the dram ball. v ref is v ref dq for dq and dm inputs. 2. input setup timing parameters ( t is and t ds) are referenced at v il ( ac )/v ih ( ac ), not v ref ( dc ). 3. input hold timing parameters ( t ih and t dh) are referenced at v il ( dc )/v ih ( dc ), not v ref ( dc ). 4. single-ended input slew rate = 1 v/ns; maxi mum input voltage swing under test is 900mv (peak-to-peak). 5. for v ih ( ac ) and v il ( ac ) levels of 150mv, special setup and hold derating and different t vac numbers apply. table 22: ac input operating conditions parameter/condition symbol ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 units command and address input high ac voltage: logic 1 v ih ( ac ) min +175 +150 or +175 mv input high dc voltage: logic 1 v ih ( dc ) min +100 +100 mv input low dc voltage: logic 0 v il ( dc ) max ?100 ?100 mv input low ac voltage: logic 0 v il ( ac ) max ?175 ?150 or ?175 mv dq and dm input high ac voltage: logic 1 v ih ( ac ) min +175 +150 mv input high dc voltage: logic 1 v ih ( dc ) min +100 +100 mv input low dc voltage: logic 0 v il ( dc ) max ?100 ?100 mv input low ac voltage: logic 0 v il ( ac ) max ?175 ?150 mv
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_3.fm - rev. d 8/1/08 en 42 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram electrical specifications ? dc and ac figure 17: input signal notes: 1. numbers in diagrams reflect nominal values. ac overshoot/undershoot specification table 23: control and address pins parameter ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 maximum peak amplitude allowed for overshoot area (see figure 18 on page 43) 0.4v 0.4v 0.4v 0.4v maximum peak amplitude allowed for undershoot area (see figure 19 on page 43) 0.4v 0.4v 0.4v 0.4v maximum overshoot area above v dd (see figure 18 on page 43) 0.67 vns 0.5 vns 0.4 vns 0.33 vns maximum undershoot area below v ss (see figure 19 on page 43) 0.67 vns 0.5 vns 0.4 vns 0.33 vns 0.575v 0.0v 0. 6 50v 0.720v 0.735v 0.750v 0.7 6 5v 0.780v 0.850v 0.925v v il ( a c ) v il ( d c ) v ref - a c noise v ref - d c error v ref + d c error v ref + a c noise v ih ( d c ) v ih ( a c ) 1.50v 1.90v ?0.40v v dd q v dd q + 0.4v narrow pulse wi d th v ss - 0.4v narrow pulse wi d th v ss 0.575v 0. 6 50v 0.720v 0.735v 0.750v 0.7 6 5v 0.780v 0.850v 0.925v minimum v il an d v ih levels v ih ( d c ) v ih ( a c ) v il ( a c ) v il ( d c ) v il an d v ih levels with rin gb a c k
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_3.fm - rev. d 8/1/08 en 43 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram electrical specifications ? dc and ac figure 18: overshoot figure 19: undershoot table 24: clock, data, strobe, and mask pins parameter ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 maximum peak amplitude allowed for overshoot area (see figure 18 on page 43) 0.4v 0.4v 0.4v 0.4v maximum peak amplitude allowed for undershoot area (see figure 19 on page 43) 0.4v 0.4v 0.4v 0.4v maximum overshoot area above v dd /v dd q (see figure 18 on page 43) 0.25 vns 0.19 vns 0.15 vns 0.13 vns maximum undershoot area below v ss /v ss q (see figure 19 on page 43) 0.25 vns 0.19 vns 0.15 vns 0.13 vns maximum amplitude overshoot area v dd /v dd q time (ns) volts (v) maximum amplitu d e un d ershoot area v ss /v ss q time (n s ) volt s (v)
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_3.fm - rev. d 8/1/08 en 44 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram electrical specifications ? dc and ac notes: 1. v mp ( dc ) specifies the input differen tial common mode voltage (v tr + v cp )/2 where v tr is the true input (ck, dqs) level and v cp is the complementary input (ck#, dqs#) level. v mp ( dc ) is expected to be about 0.5 v dd q. 2. the typical value of v ix ( ac ) is expected to be about 0.5 v dd of the transmitting device, and v ix ( ac ) is expected to track variations in v dd . v ix ( ac ) indicates the voltage at which dif- ferential input signals must cross. 3. reference is v ref ca( dc ) for clock and for v ref dq( dc ) for strobe. 4. clock is referenced to v dd and v ss . data strobe is referenced to v dd q and v ss q. 5. differential input slew rate = 2 v/ns. 6. the v ix extended range (175mv) is allowed on ly for the clock. additionally, the v ix extended range is only allowed when the foll owing conditions are me t: the single-ended input signals are monotonic, ha ve the single-ended swing v sel , v seh of at least v dd /2 250mv, and the differential slew rate of ck, ck# is greater than 3 v/ns. figure 20: single-ended requirements for differential signals table 25: differential input operating conditions (ck, ck# and dqs, dqs#) all voltages are referenced to v ss parameter/condition symbol min max units differential input voltage v in ?400 v dd + 400 mv differential input midpoint voltage v mp ( dc )650 850 mv differential input voltage logic high v ihdiff 200 v dd + 400 mv differential input voltage logic low v ildiff v ss q - 400 ?200 mv differential input cros sing voltage relative to v dd /2 for ck, ck# v ix v ref ( dc ) - 150 v ref ( dc ) + 150 mv v ref ( dc ) - 175 v ref ( dc ) + 175 mv differential input cros sing voltage relative to v dd /2 for dqs, dqs# v ref ( dc ) - 150 v ref ( dc ) + 150 mv v ss or v ss q v dd or v dd q v s el (max) v s eh (min) v s eh v s el v dd /2 or v dd q/2 c k or dq s
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_3.fm - rev. d 8/1/08 en 45 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram electrical specifications ? dc and ac figure 21: definition of differential ac-swing and t dvac table 26: allowed time before ringback ( t dvac) for ck - ck# and dqs - dqs# below v il ( ac ) slew rate (v/ns) t dvac (ps) at |v ihdiff ( ac )/v ildiff ( ac )| 350mv 300mv >4.0 75 175 4.0 57 170 3.0 50 167 2.0 38 163 1.9 34 162 1.6 29 161 1.4 22 159 1.2 13 155 1.0 0 150 <1.0 0 150 v ihdiff ( a c ) min v ihdiff ( d c ) min 0.0 v ildiff ( d c ) max v ildiff (max) t dva c v ihdiff (min) v ildiff ( a c ) max half c y c le t dva c c k - c k# dq s - dq s #
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_3.fm - rev. d 8/1/08 en 46 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram electrical specifications ? dc and ac slew rate definitions for single-ended input signals setup ( t is and t ds) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of v ref and the first crossing of v ih ( ac ) min. setup ( t is and t ds) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ref and the first crossing of v il ( ac ) max (see figure 22 on page 47). hold ( t ih and t dh) nominal slew rate for a rising si gnal is defined as the slew rate between the last crossing of v il ( dc ) max and the first crossing of v ref . hold ( t ih and t dh) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ih ( dc ) min and the first crossing of v ref (see figure 22 on page 47). table 27: single-ended inpu t slew rate definition input slew rates (linear signals) measured calculation input edge from to setup rising v ref v ih ( ac ) min falling v ref v il ( ac ) max hold rising v il ( dc ) max v ref falling v ih ( dc ) min v ref v ih ( a c ) min - v ref tr s v ref - v il ( a c ) max tf s v ref - v il ( d c ) max tfh v ih ( d c ) min - v ref tr s h
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_3.fm - rev. d 8/1/08 en 47 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram electrical specifications ? dc and ac figure 22: nominal slew rate definiti on for single-ended input signals trs tfs trh tfh v ref dq or v ref ca v ih ( ac ) min v ih ( dc ) min v il ( ac ) max v il ( dc ) max v ref dq or v ref ca v ih ( ac ) min v ih ( dc ) min v il ( ac ) max v il ( dc ) max setup hold single-ended input voltage (dq, cmd, addr) single-ended input voltage (dq, cmd, addr)
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_3.fm - rev. d 8/1/08 en 48 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram electrical specifications ? dc and ac slew rate definitions for differential input signals input slew rate for differential signals (ck, ck# and dqs, dqs#) are defined and measured, as shown in table 28 and figure 23. the nominal slew rate for a rising signal is defined as the slew rate between v il ( diff ) max and v ih ( diff ) min. the nominal slew rate for a falling signal is defi ned as the slew rate between v ih ( diff )min and v il ( diff )max. figure 23: nominal differential input slew ra te definition for dqs, dqs# and ck, ck# table 28: differential input slew rate definition differential input slew rates (linear signals) measured calculation input edge from to ck and dqs reference rising v il ( diff ) max v ih ( diff ) min falling v ih ( diff ) min v il ( diff ) max v ih ( diff ) min - v il ( diff ) max tr( diff ) v ih ( diff ) min - v il ( diff ) max tf( diff ) tr diff tf diff v ih ( diff ) min v il ( diff ) max 0 differential input voltage (dqs, dqs#; ck, ck#)
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_3.fm - rev. d 8/1/08 en 49 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram odt characteristics odt characteristics odt effective resistance r tt is defined by mr1[9, 6, and 2]. odt is applied to the dq, dm, dqs, dqs#, and tdqs, tdqs# balls (x8 devices only). the odt target values are listed in table 29 and table 30 on page 50. a functional representation of the odt is shown in figure 24. the individual pull-up and pull-down resistors (r tt pu and r tt pd ) are defined as follows: ?r tt pu = (v dd q - v out )/|i out |, under the condition that r tt pd is turned off ?r tt pd = (v out )/|i out |, under the condition that r tt pu is turned off figure 24: odt levels and i-v characteristics notes: 1. tolerance limits are applicable after prop er zq calibration has be en performed at a stable temperature and voltage (v dd q = v dd , v ss q = v ss ). refer to "odt sensitivity" on page 50 if either the temperature or voltage changes after calibration. 2. measurement definition for r tt : apply v ih ( ac ) to pin under test and measure current i[v ih ( ac )], then apply v il ( ac ) to pin under test and measure current i[v il ( ac )]: 3. measure voltage (vm) at the tested pin with no load: odt resistors table 30 on page 50 provides an overview of the odt dc electrical characteristics. the values provided are not specification requirements; however, they can be used as design guidelines to indicate what r tt is targeted to provide: ?r tt 120 is made up of r tt 120pd240 and r tt 120pu240 ?r tt 60 is made up of r tt 60pd120 and r tt 60pu120 ?r tt 40 is made up of r tt 40pd80 and r tt 40pu80 ?r tt 30 is made up of r tt 30pd60 and r tt 30pu60 ?r tt 20 is made up of r tt 20pd40 and r tt 20pu40 ta bl e 2 9 : on -d ie te r mi na t i on d c electrical characteristics parameter/condition symbol min nom max units notes r tt effective impedance r tt _ eff see table 30 on page 50 1, 2 deviation of vm with respect to v dd q/2 vm ?5 +5 % 1, 2, 3 r tt pu r tt pd odt chip in termination mode v dd q dq v ss q i out = i pd - i pu i pu i pd i out v out to other circuitry such as rcv, . . . r tt v ih ac () v il ac () ? | iv ih ac () () iv il ac () () | ? -------------------------------------------------------------- = vm 2vm v dd q ----------------- - 1 ? ?? ?? 100 =
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_3.fm - rev. d 8/1/08 en 50 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram odt characteristics notes: 1. values assume an rzq of 240 (1 percent). odt sensitivity if either the temperature or voltage changes after i/o calibration, the tolerance limits listed in table 29 on page 49 and table 30 can be expected to widen according to tables 31 and 32 on page 51. table 30: r tt effective impedances mr1 [9, 6, 2] r tt resistor v out min nom max units 0, 1, 0 120 r tt 120pd240 0.2 v dd q 0.6 1.0 1.1 rzq/1 0.5 v dd q 0.9 1.0 1.1 rzq/1 0.8 v dd q 0.9 1.0 1.4 rzq/1 r tt 120pu240 0.2 v dd q 0.9 1.0 1.4 rzq/1 0.5 v dd q 0.9 1.0 1.1 rzq/1 0.8 v dd q 0.6 1.0 1.1 rzq/1 120 v il ( ac ) to v ih ( ac ) 0.9 1.0 1.6 rzq/2 0, 0, 1 60 r tt 60pd120 0.2 v dd q 0.6 1.0 1.1 rzq/2 0.5 v dd q 0.9 1.0 1.1 rzq/2 0.8 v dd q 0.9 1.0 1.4 rzq/2 r tt 60pu120 0.2 v dd q 0.9 1.0 1.4 rzq/2 0.5 v dd q 0.9 1.0 1.1 rzq/2 0.8 v dd q 0.6 1.0 1.1 rzq/2 60 v il ( ac ) to v ih ( ac ) 0.9 1.0 1.6 rzq/4 0, 1, 1 40 r tt 40pd80 0.2 v dd q 0.6 1.0 1.1 rzq/3 0.5 v dd q 0.9 1.0 1.1 rzq/3 0.8 v dd q 0.9 1.0 1.4 rzq/3 r tt 40pu80 0.2 v dd q 0.9 1.0 1.4 rzq/3 0.5 v dd q 0.9 1.0 1.1 rzq/3 0.8 v dd q 0.6 1.0 1.1 rzq/3 40 v il ( ac ) to v ih ( ac ) 0.9 1.0 1.6 rzq/6 1, 0, 1 30 r tt 30pd60 0.2 v dd q 0.6 1.0 1.1 rzq/4 0.5 v dd q 0.9 1.0 1.1 rzq/4 0.8 v dd q 0.9 1.0 1.4 rzq/4 r tt 30pu60 0.2 v dd q 0.9 1.0 1.4 rzq/4 0.5 v dd q 0.9 1.0 1.1 rzq/4 0.8 v dd q 0.6 1.0 1.1 rzq/4 30 v il ( ac ) to v ih ( ac ) 0.9 1.0 1.6 rzq/8 1, 0, 0 20 r tt 20pd40 0.2 v dd q 0.6 1.0 1.1 rzq/6 0.5 v dd q 0.9 1.0 1.1 rzq/6 0.8 v dd q 0.9 1.0 1.4 rzq/6 r tt 20pu40 0.2 v dd q 0.9 1.0 1.4 rzq/6 0.5 v dd q 0.9 1.0 1.1 rzq/6 0.8 v dd q 0.6 1.0 1.1 rzq/6 20 v il ( ac ) to v ih ( ac ) 0.9 1.0 1.6 rzq/12
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_3.fm - rev. d 8/1/08 en 51 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram odt characteristics notes: 1. t = t - t(@ calibration), v = v dd q - v dd q(@ calibration) and v dd = v dd q. notes: 1. t = t - t(@ calibration), v = v dd q - v dd q(@ calibration) and v dd = v dd q. odt timing definitions odt loading differs from that used in ac timing measurements. the reference load for odt timings is shown in figure 25. two para meters define when odt turns on or off synchronously, two define when odt turn s on or off asynchronously, and another defines when odt turns on or off dynamically. table 33 outlines and provides definition and measurement reference settings for each parameter (see figure 34 on page 52). odt turn-on time begins when the output le aves high-z and odt resistance begins to turn on. odt turn-off time begins when th e output leaves low-z and odt resistance begins to turn off. figure 25: odt timing reference load table 31: odt sensitivity definition symbol min max units r tt 0.9 - dr tt dt |dt| - dr tt dv |dv| 1.6 + dr tt dt |dt| + dr tt dv |dv| rzq/(2, 4, 6, 8, 12) table 32: odt temperature and voltage sensitivity change min max units dr tt dt 0 1.5 %/c dr tt dv 0 0.15 %/mv table 33: odt timing definitions symbol begin point definition end point definition figure t aon rising edge of ck - ck# defined by the end point of odtl on extrapolated point at v ss q figure 26 on page 52 t aof rising edge of ck - ck# defined by the end point of odtl off extrapolated point at v rtt _ nom figure 26 on page 52 t aonpd rising edge of ck - ck# with odt first being registered high extrapolated point at v ss q figure 27 on page 53 t aofpd rising edge of ck - ck# with odt first being registered low extrapolated point at v rtt _ nom figure 27 on page 53 t adc rising edge of ck - ck# defined by the end point of odtl cnw , odtl cwn 4, or odtl cwn 8 extrapolated points at v rtt _ wr and v rtt _ nom figure 28 on page 53 timin g referen c e point dq, dm dq s , dq s # tdq s , tdq s # dut v ref v tt = v ss q v dd q/2 zq rzq = 240 v ss q r tt = 25 c k, c k#
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_3.fm - rev. d 8/1/08 en 52 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram odt characteristics notes: 1. assume an rzq of 240 (1 percent) and that proper zq calibration has been performed at a stable temperature and voltage (v dd q = v dd , v ss q = v ss ). figure 26: t aon and t aof definitions table 34: reference settings fo r odt timing measurements measured parameter r tt _ nom setting r tt _ wr setting v sw 1 v sw 2 t aon rzq/4 (60 ) n/a 50mv 100mv rzq/12 (20 ) n/a 100mv 200mv t aof rzq/4 (60 ) n/a 50mv 100mv rzq/12 (20 ) n/a 100mv 200mv t aonpd rzq/4 (60 ) n/a 50mv 100mv rzq/12 (20 ) n/a 100mv 200mv t aofpd rzq/4 (60 ) n/a 50mv 100mv rzq/12 (20 ) n/a 100mv 200mv t adc rzq/12 (20 )rzq/2 (120 ) 200mv 300mv c k c k# t aon v ss q dq, dm dq s , dq s # tdq s , tdq s # be g in point: risin g e dg e of c k - c k# d efine d b y the en d point of odtl on v s w 1 en d point: extrapolate d point at v ss q t s w 1 t s w 2 c k c k# v dd q/2 t aof be g in point: risin g e dg e of c k - c k# d efine d b y the en d point of odtl off en d point: extrapolate d point at v rtt _ nom v rtt _ nom v ss q t aon t aof v s w 2 v s w 2 v s w 1 t s w 1 t s w 1
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_3.fm - rev. d 8/1/08 en 53 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram odt characteristics figure 27: t aonpd and t aofpd definition figure 28: t adc definition c k c k# t aonpd v ss q dq, dm dq s , dq s # tdq s , tdq s # be g in point: risin g e dg e of c k - c k# with odt first re g istere d hi g h v s w 1 en d point: extrapolate d point at v ss q t s w 2 c k c k# v dd q/2 t aofpd be g in point: risin g e dg e of c k - c k# with odt first re g istere d low en d point: extrapolate d point at v rtt _ nom v rtt _ nom v ss q t aonpd t aofpd t s w 1 t s w 2 t s w 1 v s w 2 v s w 2 v s w 1 c k c k# t ad c dq, dm dq s , dq s # tdq s , tdq s # en d point: extrapolate d point at v rtt _ nom t s w 21 t ad c en d point: extrapolate d point at v rtt _ wr v dd q/2 v ss q v rtt _ nom v rtt _ wr v rtt _ nom be g in point: risin g e dg e of c k - c k# d efine d b y the en d point of odtl c nw be g in point: risin g e dg e of c k - c k# d efine d b y the en d point of odtl c wn 4 or odtl c wn 8 t s w 11 v s w 1 v s w 2 t s w 12 t s w 22
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_3.fm - rev. d 8/1/08 en 54 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram output driver impedance output driver impedance the output driver impedance is selected by mr1[5,1] during initialization. the selected value is able to maintain the tight toleran ces specified if proper zq calibration is performed. output specifications refer to th e default output driver unless specifically stated otherwise. a functional representation of the output buffer is shown in figure 29 on page 54. the output driver impedance r on is defined by the value of the external reference resistor rzq as follows: ?r on x =rzq/ y (with rzq = 240 1 percent; x = 34 or 40 with y = 7 or 6, respec- tively) the individual pull-up and pull-down resistors (r on pu and r on pd ) are defined as follows: ?r on pu = (v dd q - v out )/|i out |, when r on pd is turned off ?r on pd = (v out )/|i out |, when r on pu is turned off figure 29: output driver 34 output driver impedance the 34 driver (mr1[5, 1] = 01) is the default dr iver. unless otherwise stated, all timings and specifications listed herein apply to the 34 driver only. its impedance r on is defined by the value of the external reference resistor rzq as follows: r on 34 =rzq/7 (with nominal rzq = 240 1 percent) and is actually 34.3 1 percent. the 34 output driver impedance characteristics are listed in table 35 on page 55. r on pu r on pd output driver to other circuitry such as rcv, . . . chip in drive mode v dd q v ss q i pu i pd i out v out dq
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_3.fm - rev. d 8/1/08 en 55 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram output driver impedance notes: 1. tolerance limits assume rzq of 240 (1 percent) and are applic able after proper zq cali- bration has been performed at a stable temperature and voltage (v dd q = v dd , v ss q=v ss ). refer to "34 driver output sensitivity" on page 56 if either the temperature or the volt- age changes after calibration. 2. measurement definition for mismatch between pull-up and pull-down (mm pupd ). measure both r on pu and r on pd at 0.5 v dd q: 34 driver the 34 driver?s current range has been calculated and summarized in table 37 on page 56 for v dd = 1.5v, table 38 on page 56 for v dd = 1.575v, and table 39 on page 56 for v dd = 1.425v. the individual pull -up and pull-down resistors (r on 34pd and r on 34pu ) are defined as follows: ?r on 34pd = (v out )/|i out |; r on 34pu is turned off ?r on 34pu = (v dd q - v out )/|i out |; r on 34pd is turned off table 35: 34 driver impedance characteristics mr1[5,1] r on resistor v out min nom max units notes 0,1 34.3 ron 34pd 0.2/v dd q0.6 1.0 1.1 rzq / 71 0.5/v dd q0.9 1.0 1.1 rzq / 71 0.8/v dd q0.9 1.0 1.4 rzq / 71 r on 34pu 0.2/v dd q0.9 1.0 1.4 rzq / 71 0.5/v dd q0.9 1.0 1.1 rzq / 71 0.8/v dd q0.6 1.0 1.1 rzq / 71 pull-up/pull-down mismatch (mm pupd ) 0.5/v dd q ?10% n/a 10 % 1, 2 table 36: 34 driver pull-up and pull-down impedance calculations r on min nom max units rzq = 240 1 percent 237.6 240 242.4 rzq/7 = (240 1 percent)/7 33.9 34.3 34.6 mr1[5,1] r on resistor v out min nom max units 0, 1 34.3 r on 34pd 0.2 v dd q 20.4 34.3 38.1 0.5 v dd q 30.5 34.3 38.1 0.8 v dd q 30.5 34.3 48.5 r on 34pu 0.2 v dd q 30.5 34.3 48.5 0.5 v dd q 30.5 34.3 38.1 0.8 v dd q 20.4 34.3 38.1 mm pupd r on pu r on pd ? r on n om --------------------- --------------- x 100 =
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_3.fm - rev. d 8/1/08 en 56 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram output driver impedance 34 driver output sensitivity if either the temperature or the voltage change s after zq calibration, the tolerance limits listed in table 35 on page 55 can be expected to widen according to table 40 and table 41 on page 57. notes: 1. t = t - t(@ calibration), v = v dd q - v dd q(@ calibration), and v dd = v dd q. table 37: 34 driver i oh /i ol characteristics: v dd = v dd q = 1.5v mr1[5,1] r on resistor v out max nom min units 0, 1 34.3 r on 34pd i ol @ 0.2 v dd q14.7 8.8 7.9 ma i ol @ 0.5 v dd q 24.6 21.9 19.7 ma i ol @ 0.8 v dd q 39.3 35.0 24.8 ma r on 34pu i oh @ 0.2 v dd q 39.3 35.0 24.8 ma i oh @ 0.5 v dd q 24.6 21.9 19.7 ma i oh @ 0.8 v dd q14.7 8.8 7.9 ma table 38: 34 driver i oh /i ol characteristics: v dd = v dd q = 1.575v mr1[5,1] r on resistor v out max nom min units 0, 1 34.3 r on 34pd i ol @ 0.2 v dd q15.5 9.2 8.3 ma i ol @ 0.5 v dd q 25.8 23 20.7 ma i ol @ 0.8 v dd q 41.2 36.8 26 ma r on 34pu i oh @ 0.2 v dd q 41.2 36.8 26 ma i oh @ 0.5 v dd q 25.8 23 20.7 ma i oh @ 0.8 v dd q15.5 9.2 8.3 ma table 39: 34 driver i oh /i ol characteristics: v dd = v dd q = 1.425v mr1[5,1] r on resistor v out max nom min units 0, 1 34.3 r on 34pd i ol @ 0.2 v dd q14.0 8.3 7.5 ma i ol @ 0.5 v dd q 23.3 20.8 18.7 ma i ol @ 0.8 v dd q 37.3 33.3 23.5 ma r on 34pu i oh @ 0.2 v dd q 37.3 33.3 23.5 ma i oh @ 0.5 v dd q 23.3 20.8 18.7 ma i oh @ 0.8 v dd q14.0 8.3 7.5 ma table 40: 34 output driver sen sitivity definition symbol min max units r on @ 0.8 v dd q 0.9 - dr on dth | t| - dr on dvh | v| 1.1 + dr on dth | t| + dr on dvh | v| rzq / 7 r on @ 0.5 v dd q 0.9 - dr on dtm | t| - dr on dvm | v| 1.1 + dr on dtm | t| + dr on dvm | v| rzq/7 r on @ 0.2 v dd q 0.9 - dr on dtl | t| - dr on dvl | v| 1.1 + dr on dtl | t| + dr on dvl| v| rzq / 7
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_3.fm - rev. d 8/1/08 en 57 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram output driver impedance alternative 40 driver notes: 1. tolerance limits assume rzq of 240 (1 percent) and are applic able after proper zq cali- bration has been performed at a st able temperature and voltage (v dd q = v dd , v ss q = v ss ). refer to "40 driver output sensitivity" on page 57 if either the temperature or the volt- age changes after calibration. 2. measurement definition for mismatch between pull-up and pull-down (mm pupd ). measure both r on pu and r on pd at 0.5 v dd q: 40 driver output sensitivity if either the temperature or the voltage ch anges after i/o calibration, the tolerance limits listed in table 42 can be expected to widen according to table 43 and table 44 on page 58. notes: 1. t = t - t(@ calibration), v = v dd q - v dd q(@ calibration), and v dd = v dd q. table 41: 34 output driver voltage and temperature sensitivity change min max units dr on dtm 0 1.5 %/c dr on dvm 0 0.13 %/mv dr on dtl 0 1.5 %/c dr on dvl 0 0.13 %/mv dr on dth 0 1.5 %/c dr on dvh 0 0.13 %/mv table 42: 40 driver impedance characteristics mr1[5,1] r on resistor v out min nom max units notes 0,0 40 r on 40pd 0.2 v dd q 0.6 1.0 1.1 rzq/6 1, 2 0.5 v dd q 0.9 1.0 1.1 rzq/6 1, 2 0.8 v dd q 0.9 1.0 1.4 rzq/6 1, 2 r on 40pu 0.2 v dd q 0.9 1.0 1.4 rzq/6 1, 2 0.5 v dd q 0.9 1.0 1.1 rzq/6 1, 2 0.8 v dd q 0.6 1.0 1.1 rzq/6 1, 2 pull-up/pull-down mismatch (mm pupd )0.5v dd q ?10% n/a 10 % 1, 2 table 43: 40 output driver sen sitivity definition symbol min max units r on @ 0.8 v dd q 0.9 - dr on dth | t| - dr on dvh | v| 1.1 + dr on dth | t| + dr on dvh | v| rzq/6 r on @ 0.5 v dd q 0.9 - dr on dtm | t| - dr on dvm | v| 1.1 + dr on dtm | t| + dr on dvm | v| rzq/6 r on @ 0.2 v dd q 0.9 - dr on dtl | t| - dr on dvl | v| 1.1 + dr on dtl | t| + dr on dvl| v| rzq/6 mm pupd r on pu r on pd ? r on nom -------------------- ---------------- - x 100 =
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_3.fm - rev. d 8/1/08 en 58 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram output characteristics and operating conditions output characteristics and operating conditions the dram uses both single-ended and diffe rential output drivers. the single-ended output driver is summarized in table 45 wh ile the differential output driver is summa- rized in table 46 on page 59. notes: 1. rzq of 240 (1 percent) with rzq/7 enabled (default 34 driver) and is applicable after proper zq calibration has been performe d at a stable temperature and voltage (v dd q=v dd , v ss q=v ss ). 2. v tt = v dd q/2. 3. see figure 32 on page 60 for the test load configuration. 4. see table 35 on page 55 for iv curve linearity. do not use ac test load. 5. see table 47 on page 61 for output slew rate. 6. see table 35 on page 55 fo r additional information. 7. see figure 30 on page 59 for an exampl e of a single-ended output signal. table 44: 40 output driver voltage and temperature sensitivity change min max unit dr on dtm 0 1.5 %/c dr on dvm 0 0.15 %/mv dr on dtl 0 1.5 %/c dr on dvl 0 0.15 %/mv dr on dth 0 1.5 %/c dr on dvh 0 0.15 %/mv table 45: single-ended output driver characteristics all voltages are referenced to vss parameter/condition symbol min max units notes output leakage current: dq are disabled; 0v v out v dd q; odt is disabled; odt is high i oz ?5 +5 a 1 output slew rate: single-e nded; for rising and falling edges, measure between v ol ( ac ) = v ref - 0.1 v dd q and v oh ( ac )=v ref +0.1v dd q srq se 2.5 5 v/ns 1, 2, 3 single-ended dc high-level output voltage v oh ( dc )0.8v dd qv1, 2, 4 single-ended dc mid-point level output voltage v om ( dc )0.5v dd qv1, 2, 4 single-ended dc low-level output voltage v ol ( dc )0.2v dd qv1, 2, 4 single-ended ac high-level output voltage v oh ( ac )v tt + 0.1 v dd q v 1, 2, 3, 5 single-ended ac low-level output voltage v ol ( ac )v tt - 0.1 v dd q v 1, 2, 3, 5 delta r on between pull-up and pull-down for dq/dqs mm pupd ?10 +10 % 1, 6 test load for ac timing and ou tput slew rates output to v tt (v dd q/2) via 25 resistor 3
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_3.fm - rev. d 8/1/08 en 59 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram output characteristics and operating conditions notes: 1. rzq of 240 (1 percent) with rzq/7 enabled (default 34 driver) and is applicable after proper zq calibration has been performe d at a stable temperature and voltage (v dd q=v dd , v ss q=v ss ). 2. v ref = v dd q/2. 3. see figure 32 on page 60 for the test load configuration. 4. see table 48 on page 62 for the output slew rate. 5. see table 35 on page 55 fo r additional information. 6. see figure 31 on page 60 for an exampl e of a differential output signal. figure 30: dq output signal table 46: differential output driver characteristics all voltages are referenced to vss parameter/condition symbol min max units notes output leakage current: dq are disabled; 0v v out v dd q; odt is disabled; odt is high i oz ?5 +5 a 1 output slew rate: differential; for rising and falling edges, measure between v oldiff ( ac ) = ?0.2 v dd q and v ohdiff ( ac ) = +0.2 v dd q srq diff 510v/ns1 output differential cross-point voltage v ox ( ac )v ref - 100 v ref + 100 mv 1, 2, 3 differential high-lev el output voltage v ohdiff ( ac )+0.2v dd qv1, 4 differential low-level output voltage v oldiff ( ac )?0.2v dd qv1, 4 delta r on between pull-up and pull-down for dq/dqs mm pupd ?10 +10 % 1, 5 test load for ac timing and ou tput slew rates output to v tt (v dd q/2) via 25 resistor 3 v oh ( a c ) min output max output v ol ( a c )
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_3.fm - rev. d 8/1/08 en 60 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram output characteristics and operating conditions figure 31: differential output signal reference output load figure 32 on page 60 represents the effective reference load of 25 used in defining the relevant device ac timing parameters (exc ept odt reference timing) as well as the output slew rate measurements. it is not in tended to be a precis e representation of a particular system environment or a depiction of the actual load presented by a produc- tion tester. system designers should use ibis or other simulation tools to correlate the timing reference load to a system environment. figure 32: reference output load for ac timing and output slew rate v oh ( diff ) min output max output v ol ( diff ) v ox ( a c ) max v ox ( a c ) min x x x x timin g referen c e point dq dq s dq s # dut v ref v tt = v dd q/2 v dd q/2 zq rzq = 240 v ss r tt = 25
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_3.fm - rev. d 8/1/08 en 61 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram output characteristics and operating conditions slew rate definitions for si ngle-ended output signals the single-ended output driver is summar ized in table 45 on page 58. with the refer- ence load for timing measurements, the output slew rate for falling and rising edges is defined and measured between v ol ( ac ) and v oh ( ac ) for single-ended signals, as shown in table 47 and figure 33. figure 33: nominal slew rate definiti on for single-ended output signals table 47: single-ended outp ut slew rate definition single-ended output slew rates (linear signals) measured calculation output edge from to dq rising v ol ( ac )v oh ( ac ) falling v oh ( ac )v ol ( ac ) v oh ( a c ) - v ol ( a c ) tr s e v oh ( a c ) - v ol ( a c ) tf s e tr se tf se v oh ( ac ) v ol ( ac ) v tt
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_3.fm - rev. d 8/1/08 en 62 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram output characteristics and operating conditions slew rate definitions for differential output signals the differential output driver is summarized in table 46 on page 59 . with the reference load for timing measurements, the output slew rate for falling and rising edges is defined and measured between v ol ( ac ) and v oh ( ac ) for differential signals, as shown in tabl e 48 and fi gure 34 . figure 34: nominal differential output slew rate definition for dqs, dqs# table 48: differential outp ut slew rate definition differential output slew rates (linear signals) measured calculation output edge from to dqs, dqs# rising v oldiff ( ac )v ohdiff ( ac ) falling v ohdiff ( ac )v oldiff ( ac ) v ohdiff ( a c ) - v oldiff ( a c ) tr diff v ohdiff ( a c ) - v oldiff ( a c ) tf diff tr diff tf diff v oh ( diff ) ac v ol ( diff ) ac 0
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_3.fm - rev. d 8/1/08 en 63 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram speed bin tables speed bin tables notes: 1. t refi depends on t oper . 2. the cl and cwl settings result in t ck re q uirements. when making a selection of t ck, both cl and cwl re q uirement settings need to be fulfilled. 3. reserved settings are not allowed. table 49: ddr3-800 speed bins ddr3-800 speed bin -25e -25 units notes cl- t rcd- t rp 5-5-5 6-6-6 parameter symbol min max min max activate to internal read or write delay time t rcd 12.5 ? 15 ? ns precharge command period t rp 12.5 ? 15 ? ns activate-to-activate or refresh command period t rc 50 ? 52.5 ? ns activate-to-prechar ge command period t ras 37.5 9 t refi 37.5 9 t refi ns 1 cl = 5 cwl = 5 t ck (avg) 2.5 3.3 reserved ns 2, 3 cl = 6 cwl = 5 t ck (avg) 2.5 3.3 2.5 3.3 ns 2 supported cl settings 5, 6 6 ck supported cwl settings 5 5 ck
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_3.fm - rev. d 8/1/08 en 64 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram speed bin tables notes: 1. t refi depends on t oper . 2. the cl and cwl settings result in t ck re q uirements. when making a selection of t ck, both cl and cwl re q uirement settings need to be fulfilled. 3. reserved settings are not allowed. table 50: ddr3-1066 speed bins ddr3-1066 speed bin -187e -187 units notes cl- t rcd- t rp 7-7-7 8-8-8 parameter symbol min max min max activate to internal read or write delay time t rcd 13.125 ? 15 ? ns precharge command period t rp 13.125 ? 15 ? ns activate-to-activate or refresh command period t rc 50.625 ? 52.5 ? ns activate-to-prec harge command period t ras 37.5 9 t refi 37.5 9 t refi ns 1 cl = 5 cwl = 5 t ck (avg) reserved reserved ns 2, 3 cwl = 6 t ck (avg) reserved reserved ns 3 cl = 6 cwl = 5 t ck (avg) 2.5 3.3 2.5 3.3 ns 2 cwl = 6 t ck (avg) reserved reserved ns 2, 3 cl = 7 cwl = 5 t ck (avg) reserved reserved ns 3 cwl = 6 t ck (avg) 1.875 <2.5 reserved ns 2, 3 cl = 8 cwl = 5 t ck (avg) reserved reserved ns 3 cwl = 6 t ck (avg) 1.875 <2.5 1.875 <2.5 ns 2 supported cl settings 6, 7, 8 6, 8 ck supported cwl settings 5, 6 5, 6 ck
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_3.fm - rev. d 8/1/08 en 65 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram speed bin tables notes: 1. t refi depends on t oper . 2. the cl and cwl settings result in t ck re q uirements. when making a selection of t ck, both cl and cwl re q uirement settings need to be fulfilled. 3. reserved settings are not allowed. table 51: ddr3-1333 speed bins ddr3-1333 speed bin -15f -15e -15 units notes cl- t rcd- t rp 8-8-8 9-9-9 10-10-10 parameter symbol min max min max min max activate to internal read or write delay time t rcd12?13.5?15?ns precharge command period t rp 12 ? 13.5 ? 15 ? ns activate-to-activate or refresh command period t rc 48 ? 49.5 ? 51 ? ns activate-to-precharge command period t ras 36 9 t refi 36 9 t refi 36 9 t refi ns 1 cl = 5 cwl = 5 t ck (avg) 2.5 3.3 reserved reserved ns 2, 3 cwl = 6, 7 t ck (avg) reserved reserved reserved ns 3 cl = 6 cwl = 5 t ck (avg) 2.5 3.3 2.5 3.3 2.5 3.3 ns 2 cwl = 6 t ck (avg) reserved reserved reserved ns 2, 3 cwl = 7 t ck (avg) reserved reserved reserved ns 3 cl = 7 cwl = 5 t ck (avg) reserved reserved reserved ns 3 cwl = 6 t ck (avg) 1.875 <2.5 1.875 <2.5 reserved ns 2, 3 cwl = 7 t ck (avg) reserved reserved reserved ns 2, 3 cl = 8 cwl = 5 t ck (avg) reserved reserved reserved ns 3 cwl = 6 t ck (avg) 1.875 <2.5 1.875 <2.5 1.875 <2.5 ns 2 cwl = 7 t ck (avg) 1.5 <1.875 reserved reserved ns 2, 3 cl = 9 cwl = 5, 6 t ck (avg) reserved reserved reserved ns 3 cwl = 7 t ck (avg) 1.5 <1.875 1.5 <1.875 reserved ns 2, 3 cl = 10 cwl = 5, 6 t ck (avg) reserved reserved reserved ns 3 cwl = 7 t ck (avg) 1.5 <1.875 1.5 <1.875 1.5 <1.875 ns 2 supported cl settings 5, 6, 7, 8, 9, 10 6, 7, 8, 9, 10 6, 8, 10 ck supported cwl settings 5, 6, 7 5, 6, 7 5, 6, 7 ck
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_3.fm - rev. d 8/1/08 en 66 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram speed bin tables notes: 1. t refi depends on t oper . 2. the cl and cwl settings result in t ck re q uirements. when making a selection of t ck, both cl and cwl re q uirement settings need to be fulfilled. 3. reserved settings are not allowed. table 52: ddr3-1600 speed bins ddr3-1600 speed bin -125f -125e -125 units notes cl- t rcd- t rp 9-9-9 10-10-10 11-11-11 parameter symbol min max min max min max activate to internal read or write delay time t rcd 11.25 ? 12.5 ? 13.75 ? ns precharge command period t rp 11.25 ? 12.5 ? 13.75 ? ns activate-to-activate or refresh command period t rc 46.25 ? 47.5 ? 48.75 ? ns activate-to-precharge command period t ras 35 9 t refi 35 9 t refi 35 9 t refi ns 1 cl = 5 cwl = 5 t ck (avg) 2.5 3.3 2.5 3.3 reserved ns 2, 3 cwl = 6, 7, 8 t ck (avg) reserved reserved reserved ns 3 cl = 6 cwl = 5 t ck (avg) 2.5 3.3 2.5 3.3 2.5 3.3 ns 2 cwl = 6 t ck (avg) reserved reserved reserved ns 2, 3 cwl = 7, 8 t ck (avg) reserved reserved reserved ns 3 cl = 7 cwl = 5 t ck (avg) reserved reserved reserved ns 3 cwl = 6 t ck (avg) 1.875 <2.5 1.875 <2.5 reserved ns 2, 3 cwl = 7 t ck (avg) reserved reserved reserved ns 2, 3 cwl = 8 t ck (avg) reserved reserved reserved ns 3 cl = 8 cwl = 5 t ck (avg) reserved reserved reserved ns 3 cwl = 6 t ck (avg) 1.875 <2.5 1.875 <2.5 1.875 <2.5 ns 2 cwl = 7 t ck (avg) 1.5 <1.875 reserved reserved ns 2, 3 cwl = 8 t ck (avg) reserved reserved reserved ns 2, 3 cl = 9 cwl = 5, 6 t ck (avg) reserved reserved reserved ns 3 cwl = 7 t ck (avg) 1.5 <1.875 1.5 <1.875 reserved ns 2, 3 cwl = 8 t ck (avg) 1.25 <1.5 reserved reserved ns 2, 3 cl = 10 cwl = 5, 6 t ck (avg) reserved reserved reserved ns 3 cwl = 7 t ck (avg) 1.5 <1.875 1.5 <1.875 1.5 <1.875 ns 2 cwl = 8 t ck (avg) 1.25 <1.5 1.25 <1.5 reserved ns 2, 3 cl = 11 cwl = 5, 6, 7 t ck (avg) reserved reserved reserved ns 3 cwl = 8 t ck (avg)1.25<1.51.25<1.51.25<1.5 ns 2 supported cl settings 5, 6, 7, 8, 9, 10, 11 5, 6, 7, 8, 9, 10, 11 6, 8, 10, 11 ck supported cwl settings 5, 6, 7, 8 5, 6, 7, 8 5, 6, 7, 8 ck
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_3.fm - rev. d 8/1/08 en 67 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram speed bin tables table 53: electrical characteristics and ac operating conditions (sheet 1 of 7) notes: 1?8 apply to the entire table; notes appear on page 74 parameter symbol ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 units notes min max min max min max min max clock timing clock period average: dll disable mode t c = 0c to 85c t ck dll _ dis 87,80087,80087,80087,800ns9 t c = >85c to 95c 83,90083,90083,90083,900ns clock period average: dll enable mode t ck (avg) see ?speed bin tables? on page 63 for t ck range allowed ns 10 , 11 high pulse width average t ch (avg) 0.47 0.53 0.47 0.5 30.470.530.470.53ck12 low pulse width average t cl (avg) 0.47 0.53 0.47 0.5 30.470.530.470.53ck12 clock period jitter dll locked t jit per ?100 100 ?90 90 ?80 80 ?70 70 ps 13 dll locking t jit per , lck ?90 90 ?80 80 ?70 70 ?60 60 ps 13 clock absolute period t ck(abs) min = t ck (avg) min + t jit per min; max = t ck (avg) max + t jit per max ps clock absolute high pulse width t ch (abs) 0.43 ? 0.43 ? 0.43 ? 0.43 ? t ck (avg) 14 clock absolute low pulse width t cl (abs) 0.43 ? 0.43 ? 0.43 ? 0.43 ? t ck (avg) 15 cycle-to-cycle jitter dll locked t jit cc 200 180 160 140 ps 16 dll locking t jit cc , lck 180 160 140 120 ps 16 cumulative error across 2 cycles t err 2 per ?147 147 ?132 132 ?118 118 ?103 103 ps 17 3 cycles t err 3 per ?175 175 ?157 157 ?140 140 ?122 122 ps 17 4 cycles t err 4 per ?194 194 ?175 175 ?155 155 ?136 136 ps 17 5 cycles t err 5 per ?209 209 ?188 188 ?168 168 ?147 147 ps 17 6 cycles t err 6 per ?222 222 ?200 200 ?177 177 ?155 155 ps 17 7 cycles t err 7 per ?232 232 ?209 209 ?186 186 ?163 163 ps 17 8 cycles t err 8 per ?241 241 ?217 217 ?193 193 ?169 169 ps 17 9 cycles t err 9 per ?249 249 ?224 224 ?200 200 ?175 175 ps 17 10 cycles t err 10 per ?257 257 ?231 231 ?205 205 ?180 180 ps 17 11 cycles t err 11 per ?263 263 ?237 237 ?210 210 ?184 184 ps 17 12 cycles t err 12 per ?269 269 ?242 242 ?215 215 ?188 188 ps 17 n = 13, 14 . . . 49, 50 cycles t err n per t err n per min = (1 + 0.68ln[ n ]) t jit per min t err n per max = (1 + 0.68ln[ n ]) t jit per max ps 17
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_3.fm - rev. d 8/1/08 en 68 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram speed bin tables dq input timing data setup time to dqs, dqs# base (specification) t ds ac175 75?25?????ps18, 19 v ref @ 1 v/ns 250?200?????ps19, 20 data hold time from dqs, dqs# base (specification) t dh ac175 150?100?????ps18,19 v ref @ 1 v/ns 250?200?????ps19, 20 data setup time to dqs, dqs# base (specification) t ds ac150 ????30?10?ps18, 19, 21 v ref @ 1 v/ns ????180?160?ps19, 20,21 data hold time from dqs, dqs# base (specification) t dh ac150 ????65?45?ps18, 19, 21 v ref @ 1 v/ns ????165?145?ps19, 20, 21 minimum data pulse width t dipw 600 ? 490 ? 400 ? 360 ? ps 42 dq output timing dqs, dqs# to dq skew, per access t dqsq ? 200 ? 150 ? 125 ? 100 ps dq output hold ti me from dqs, dqs# t qh 0.38 ? 0.38 ? 0.38 ? 0.38 ? t ck (avg) 22 dq low-z time from ck, ck# t lz (dq) ?800 400 ?600 300 ?500 250 ?450 225 ps 23 , 24 dq high-z time from ck, ck# t hz (dq) ? 400 ? 300 ? 250 ? 225 ps 23 , 24 dq strobe input timing dqs, dqs# rising to ck, ck# rising t dqss ?0.25 0.25 ?0.25 0.25 ?0.25 0.25 ?0.27 0.27 ck 26 dqs, dqs# differential input low pulse width t dqsl 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 ck dqs, dqs# differential input high pulse width t dqsh 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 ck dqs, dqs# falling setup to ck, ck# rising t dss 0.2 ? 0.2 ? 0.2 ? 0.18 ? ck 26 dqs, dqs# falling hold from ck, ck# rising t dsh 0.2 ? 0.2 ? 0.2 ? 0.18 ? ck 26 dqs, dqs# differen tial write preamble t wpre 0.9 ? 0.9 ? 0.9 ? 0.9 ? ck dqs, dqs# differen tial write postamble t wpst 0.3 ? 0.3 ? 0.3 ? 0.3 ? ck table 53: electrical characteristics and ac operating conditions (sheet 2 of 7) notes: 1?8 apply to the entire table; notes appear on page 74 parameter symbol ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 units notes min max min max min max min max
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_3.fm - rev. d 8/1/08 en 69 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram speed bin tables dq strobe output timing dqs, dqs# rising to/from rising ck, ck# t dqsck ?400 400 ?300 300 ?255 255 ?225 225 ps 24 dqs, dqs# rising to/fro m rising ck, ck# when dll is disabled t dqsck dll_dis 110110110110ns27 dqs, dqs# differenti al output high time t qsh 0.38 ? 0.38 ? 0.40 ? 0.40 ? ck 22 dqs, dqs# differential output low time t qsl 0.38 ? 0.38 ? 0.40 ? 0.40 ? ck 22 dqs, dqs# low-z time (rl - 1) t lz (dqs) ?800 400 ?600 300 ?500 250 ?450 225 ps 23 , 24 dqs, dqs# high-z time (rl + bl/2) t hz (dqs) ? 400 ? 300 ? 250 ? 225 ps 23 , 24 dqs, dqs# differential read preamble t rpre 0.9 note 25 0.9 note 25 0.9 note 25 0.9 note 25 ck 24 , 25 dqs, dqs# differential read postamble t rpst 0.3 note 28 0.3 note 28 0.3 note 28 0.3 note 28 ck 24 , 28 table 53: electrical characteristics and ac operating conditions (sheet 3 of 7) notes: 1?8 apply to the entire table; notes appear on page 74 parameter symbol ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 units notes min max min max min max min max
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_3.fm - rev. d 8/1/08 en 70 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram speed bin tables command and address timing dll locking time t dllk 512 ? 512 ? 512 ? 512 ? ck 29 ctrl, cmd, addr setup to ck,ck# base (specification) t is ac175 200 ? 125 ? 65 ? 45 ? ps 30, 31 v ref @ 1 v/ns 375 ? 300 ? 240 ? 220 ? ps 20, 31 ctrl, cmd, addr hold from ck,ck# base (specification) t ih 275 ? 200 ? 140 ? 120 ? ps 30, 31 v ref @ 1 v/ns 375 ? 300 ? 240 ? 220 ? ps 20, 31 ctrl, cmd, addr setup to ck,ck# base (specification) t is ac150 ????190?170?ps21, 30, 31 v ref @ 1 v/ns ????340?320?ps20, 21, 31 minimum ctrl, cmd, addr pulse width t ipw 900 ? 780 ? 620 ? 560 ? ps 42 activate to internal read or write delay t rcd see ?speed bin tables? on page 63 for t rcd ns 32 precharge command period t rp see ?speed bin tables? on page 63 for t rp ns 32 activate-to-prechar ge command period t ras see ?speed bin tables? on page 63 for t ras ns 32, 33 activate-to-activa te command period t rc see ?speed bin tables? on page 63 for t rc ns 32 activate-to- activate minimum command period 1kb page size t rrd min = greater of 4ck or 10ns min = greater of 4ck or 7.5ns min = greater of 4ck or 6ns min = greater of 4ck or 6ns ck 32 2kb page size min = greater of 4ck or 10ns min = greater of 4ck or 7.5ns ck 32 four activate windows for 1kb page size t faw 40 ? 37.5 ? 30 ? 30 ? ns 32 four activate windows for 2k b page size 50 ? 50 ? 45 ? 40 ? ns 32 write recovery time t wr min = 15ns; max = n/a ns 32, 33, 34 delay from start of internal write transaction to internal read command t wtr min = greater of 4ck or 7.5ns; max = n/a ck 32, 35 read-to-precharge time t rtp min = greater of 4ck or 7.5ns; max = n/a ck 32, 33 cas#-to-cas# command delay t ccd min = 4ck; max = n/a ck auto precharge write recovery + precharge time t dal min = wr + t rp / t ck (avg); max = n/a ck mode register set command cycle time t mrd min = 4ck; max = n/a ck mode register set command update delay t mod min = greater of 12ck or 15ns; max = n/a ck multipurpose register read burst end to mode register set for multipurpose register exit t mprr min = 1ck; max = n/a ck table 53: electrical characteristics and ac operating conditions (sheet 4 of 7) notes: 1?8 apply to the entire table; notes appear on page 74 parameter symbol ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 units notes min max min max min max min max
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_3.fm - rev. d 8/1/08 en 71 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram speed bin tables calibration timing zqcl command: long calibration time power-up and reset operation t zq init 512 ? 512 ? 512 ? 512 ? ck normal operation t zq oper 256 ? 256 ? 256 ? 256 ? ck zqcs command: short calibration time t zq cs 64 ? 64 ? 64 ? 64 ? ck initialization and reset timing exit reset from cke high to a valid command t xpr min = greater of 5ck or t rfc + 10ns; max = n/a ck begin power supply ramp to power supplies stable t v ddpr min = n/a; max = 200 ms reset# low to power supplies stable t rps min = 0; max = 200 ms reset# low to i/o and r tt high-z t ioz min = n/a; max = 20 ns 36 refresh timing refresh-to-activate or refresh command period t rfc min = 110; max = 9 t refi (refresh-to-refresh command period) ns maximum refresh period t c = 0c to 85c ? 64 (1x) ms 37 t c = >85c to 95c 32 (2x) ms 37 maximum average periodic refresh t c = 0c to 85c t refi 7.8 (64ms/8,192) s 37 t c = >85c to 95c 3.9 (32ms/8,192) s 37 self refresh timing exit self refresh to commands not re q uiring a locked dll t xs min = greater of 5ck or t rfc + 10ns; max = n/a ck exit self refresh to commands re q uiring a locked dll t xsdll min = t dllk (min); max = n/a ck 29 minimum cke low pulse width for self refresh entry to self refresh exit timing t ckesr min = t cke (min) + ck; max = n/a ck valid clocks after self refresh entry or power- down entry t cksre min = greater of 5ck or 10ns; max = n/a ck valid clocks before self refresh exit, power- down exit, or reset exit t cksrx min = greater of 5ck or 10ns; max = n/a ck table 53: electrical characteristics and ac operating conditions (sheet 5 of 7) notes: 1?8 apply to the entire table; notes appear on page 74 parameter symbol ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 units notes min max min max min max min max
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_3.fm - rev. d 8/1/08 en 72 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram speed bin tables power-down timing cke min pulse width t cke (min) greater of 3ck or 7.5ns greater of 3ck or 5.625ns greater of 3ck or 5.625ns greater of 3ck or 5ns ck command pass disable delay t cpded min = 1; max = n/a ck power-down entry to power-down exit timing t pd min = t cke (min); max = 9 t refi ck begin power-down period prior to cke registered high t anpd wl - 1ck ck power-down entry period: odt either synchronous or asynchronous pde greater of t anpd or t rfc - refresh command to cke low time ck power-down exit period: odt either synchronous or asynchronous pdx t anpd + t xpdll ck power-down entry minimum timing activate command to power-down entry t actpden min = 1 ck precharge/precharge all command to power-down entry t prpden min = 1 ck refresh command to power-down entry t refpden min = 1 ck 38 mrs command to power-down entry t mrspden min = t mod (min) ck read/read with auto pr echarge command to power-down entry t rdpden min = rl + 4 + 1 ck write command to power-down entry bl8 (otf, mrs) bc4otf t wrpden min = wl + 4 + t wr / t ck (avg) ck bc4mrs t wrpden min = wl + 2 + t wr / t ck (avg) ck write with auto precharge command to power-down entry bl8 (otf, mrs) bc4otf t wrapden min = wl + 4 + wr + 1 ck bc4mrs t wrapden min = wl + 2 + wr + 1 ck power-down exit timing dll on, any valid comma nd, or dll off to commands not re q uiring locked dll t xp min = greater of 3ck or 7.5ns; max = n/a min = greater of 3ck or 6ns; max = n/a ck precharge power-down with dll off to commands re q uiring a locked dll t xpdll min = greater of 10ck or 24ns; max = n/a ck 29 table 53: electrical characteristics and ac operating conditions (sheet 6 of 7) notes: 1?8 apply to the entire table; notes appear on page 74 parameter symbol ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 units notes min max min max min max min max
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_3.fm - rev. d 8/1/08 en 73 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram speed bin tables odt timing r tt synchronous turn-on delay odtl on cwl + al - 2ck ck 39 r tt synchronous turn-off delay odtl off cwl + al - 2ck ck 41 r tt turn-on from odtl on reference t aon ?400 400 ?300 300 ?250 250 ?225 225 ps 24 , 39 r tt turn-off from odtl off reference t aof 0.3 0.7 0.3 0.7 0.3 0.7 0.3 0.7 ck 40 , 41 asynchronous r tt turn-on delay (power-down with dll off) t aonpd min = 1; max = 9 ns 39 asynchronous r tt turn-off delay (power-down with dll off) t aofpd min = 1; max = 9 ns 41 odt high time with write command and bl8 odth8 min = 6; max = n/a ck odt high time withou t write command or with write command and bc4 odth4 min = 4; max = n/a ck dynamic odt timing r tt _ nom -to-r tt _ wr change skew odtl cnw wl - 2ck ck r tt _ wr -to-r tt _ nom change skew - bc4 odtl cnw 4 4ck + odtl off ck r tt _ wr -to-r tt _ nom change skew - bl8 odtl cnw 8 6ck + odtl off ck r tt dynamic change skew t adc 0.3 0.7 0.3 0.7 0.3 0.7 0.3 0.7 ck 40 write leveling timing first dqs, dqs# rising edge t wlmrd 40 ? 40 ? 40 ? 40 ? ck dqs, dqs# delay t wldqsen 25 ? 25 ? 25 ? 25 ? ck write leveling setup from rising ck, ck# crossing to rising dqs, dqs# crossing t wls 325 ? 245 ? 195 ? 163 ? ps write leveling hold from rising dqs, dqs# crossing to rising ck, ck# crossing t wlh 325 ? 245 ? 195 ? 163 ? ps write leveling output delay t wlo09090907.5ns write leveling output error t wloe02020202ns table 53: electrical characteristics and ac operating conditions (sheet 7 of 7) notes: 1?8 apply to the entire table; notes appear on page 74 parameter symbol ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 units notes min max min max min max min max
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_3.fm - rev. d 8/1/08 en 74 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram speed bin tables notes 1. parameters are applicable with 0c t c +95c and v dd /v dd q = +1.5v 0.075v. 2. all voltages are referenced to v ss . 3. output timings are only valid for r on 34 output buffer selection. 4. unit ? t ck (avg)? represents the actual t ck (avg) of the input clock under operation. unit ?ck? represents one clock cycle of the input clock, counting the actual clock edges. 5. ac timing and i dd tests may use a v il -to-v ih swing of up to 900mv in the test envi- ronment, but input timing is still referenced to v ref (except t is, t ih, t ds, and t dh use the ac/dc trip points and ck, ck# and dqs, dqs# use their crossing points). the minimum slew rate for the input signals used to test the device is 1 v/ns for single- ended inputs and 2 v/ns for differen tial inputs in the range between v il ( ac ) and v ih ( ac ). 6. all timings that use time-based values (ns, s, ms) should use t ck (avg) to determine the correct number of clocks (tab le 53 on page 67 uses ?ck? or ? t ck [avg]? inter- changeably). in the case of noninteger results, all minimum limits are to be rounded up to the nearest whole integer, and all ma ximum limits are to be rounded down to the nearest whole integer. 7. the use of ?strobe? or ?dqs diff ? refers to the dqs and dqs# differential crossing point when dqs is the rising edge. the use of ?clock? or ?ck? refers to the ck and ck# differential crossing point when ck is the rising edge. 8. this output load is used for all ac timing (except odt reference timing) and slew rates. the actual test load may be differen t. the output signal voltage reference point is v dd q/2 for single-ended signals and the crossing point for differential signals (see figure 32 on page 60). 9. when operating in dll disable mode, micr on does not warrant compliance with nor- mal mode timings or functionality. 10. the clock?s t ck (avg) is the average clock over any 200 consecutive clocks and t ck(avg) min is the smallest clock rate allowed, with the exception of a deviation due to clock jitter. input clock jitter is al lowed provided it does not exceed values specified and must be of a random gaussian distribution in nature. 11. spread spectrum is not included in the ji tter specification values. however, the input clock can accommodate spread-spectrum at a sweep rate in the range of 20?60 khz with an additional 1 percent of t ck (avg) as a long-term jitte r component; however, the spread-spectrum may not use a clock rate below t ck (avg) min . 12. the clock?s t ch (avg) and t cl (avg) are the average half clock period over any 200 consecutive clocks and is the smallest clock half period allowed, with the exception of a deviation due to clock jitter. input clock jitter is allowed provided it does not exceed values specified and must be of a random gaussian distribution in nature. 13. the period jitter ( t jit per ) is the maximum deviation in the clock period from the aver- age or nominal clock. it is allowed in either the positive or negative direction. 14. t ch(abs) is the absolute instantaneous cloc k high pulse width as measured from one rising edge to the following falling edge. 15. t cl(abs) is the absolute instantaneous clock low pulse width as measured from one falling edge to the following rising edge. 16. the cycle-to-cycle jitter ( t jit cc ) is the amount the clock period can deviate from one cycle to the next. it is important to keep cycle-to-cycle jitter at a minimum during the dll locking time.
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_3.fm - rev. d 8/1/08 en 75 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram speed bin tables 17. the cumulative jitter error ( t err n per ), where n is the number of clocks between 2 and 50, is the amount of clock time allowed to accumulate consecutively away from the average clock over n number of clock cycles. 18. t ds (base) and t dh (base) values are for a single-ended 1 v/ns dq slew rate and 2 v/ns differential dqs, dqs# slew rate. 19. these parameters are meas ured from a data signal (dm, dq0, dq1, and so forth) transition edge to its respective data strobe signal (dqs, dqs#) crossing. 20. the setup and hold times ar e listed converting the base specification values (to which derating tables apply) to v ref when the slew rate is 1 v/ns. these values, with a slew rate of 1 v/ns, are for reference only. 21. special setup and hold derating and different t vac numbers apply when using 150mv ac threshold. 22. when the device is operated with input cl ock jitter, this parameter needs to be der- ated by the actual t jit per of the input clock (output deratings are relative to the sdram input clock). 23. single-ended signal parameter. 24. the dram output timing is aligned to the nominal or average clock. most output parameters must be derated by the actual jitter error when input clock jitter is present, even when within specification. this results in each parameter becoming larger. the following parameters are required to be derated by subtracting t err 10per (max): t dqsck (min), t lz (dqs) min, t lz (dq) min, and t aon (min). the following parameters are required to be derated by subtracting t err 10per (min): t dqsck (max), t hz (max), t lz (dqs) max, t lz (dq) max, and t aon (max). the parameter t rpre (min) is derated by subtracting t jit per (max), while t rpre (max) is derated by subtracting t jit per (min). 25. the maximum preamble is bound by t lzdqs (max). 26. these parameters ar e measured from a data strobe si gnal (dqs, dqs#) crossing to its respective clock signal (ck, ck#) crossing. the specification values are not affected by the amount of clock jitter applied, as these are relative to the clock signal crossing. these parameters should be met whether clock jitter is present. 27. the t dqsck dll _ dis parameter begins cl + al - 1 cycles after the read command. 28. the maximum postamble is bound by t hzdqs (max). 29. commands requiring a locked dll are: read (and rdap) and synchronous odt commands. in addition, after any change of latency t xpdll, timing must be met. 30. t is (base) and t ih (base) values are for a single-ended 1 v/ns control/command/ address slew rate and 2 v/ns ck, ck# differential slew rate. 31. these parameters are meas ured from a command/address si gnal transition edge to its respective clock (ck, ck#) signal crossing. the specification values are not affected by the amount of clock jitter applied as the setup and hold times are relative to the clock signal crossing that latches the comm and/address. these parameters should be met whether clock jitter is present. 32. for these parameters, the ddr3 sdram device supports t n param ( n ck) = ru( t param [ns]/ t ck[avg] [ns]), assuming all input clock jitter specifications are sat- isfied. for example, the device will support t n rp ( n ck) = ru( t rp/ t ck[avg]) if all input clock jitter specifications are met. this means for ddr3-800 6-6-6, of which t rp = 15ns, the device will support t n rp = ru( t rp/ t ck[avg]) = 6 as long as the input clock jitter specifications are met. that is, the precharge command at t0 and the activate command at t0 + 6 are valid even if six clocks are less than 15ns due to input clock jitter. 33. during reads and writes with auto prec harge, the ddr3 sdram will hold off the internal precharge command until t ras (min) has been satisfied.
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_3.fm - rev. d 8/1/08 en 76 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram speed bin tables 34. when operating in dll disable mode, the greater of 4ck or 15ns is satisfied for t wr. 35. the start of the write recovery time is defined as follows: ? for bl8 (fixed by mrs and otf): rising clock edge four clock cycles after wl ? for bc4 (otf): rising clock edge four clock cycles after wl ? for bc4 (fixed by mrs): rising cl ock edge two cloc k cycles after wl 36. reset# should be low as soon as power starts to ramp to ensure the outputs are in high-z. until reset# is low, the outputs are at risk of driving and could result in excessive current, depending on bus activity. 37. the refresh period is 64ms. this equates to an average refresh rate of 7.8125s. how- ever, nine refresh commands must be asserted at least once every 70.3s. 38. although cke is allowed to be registered low after a refresh command when t refpden (min) is satisfied, there are cases where additional time such as t xpdll (min) is required. 39. odt turn-on time min is when the device leaves high-z and od t resistance begins to turn on. odt turn-on time maximum is when the odt resistance is fully on. the odt reference load is shown in figure 24 on page 49. 40. half-clock output parameters must be derated by the actual t err 10per and t jit dty when input clock jitter is present. this results in each parameter becoming larger. the parameters t adc (min) and t aof (min) are each required to be derated by sub- tracting both t err 10per (max) and t jit dty (max). the parameters t adc (max) and t aof (max) are required to be derated by subtracting both t err 10per (max) and t jit dty (max). 41. odt turn-off time minimum is when the device starts to turn off odt resistance. odt turn-off time maximum is when the dram buffer is in high-z. the odt refer- ence load is shown in figure 25 on page 51. th is output load is used for odt timings (see figure 32 on page 60). 42. pulse width of a input signal is defined as the width between the first crossing of v ref ( dc ) and the consecutive crossing of v ref ( dc ).
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_3.fm - rev. d 8/1/08 en 77 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram speed bin tables command and address setup, hold, and derating the total t is (setup time) and t ih (hold time) required is calculated by adding the data sheet t is (base) and t ih (base) values (see table 54; values come from table 53 on page 67) to the t is and t ih derating values (see table 55 on page 78 and table 56 on page 78), respectively. example: t is (total setup time) = t is (base) + t is. for a valid tran- sition, the input signal has to remain above/below v ih ( ac )/v il ( ac ) for some time t vac (see table 56 on page 78). although the total setup time for slow slew rates might be negative (for example, a valid input signal will not have reached v ih [ ac ]/v il [ ac ] at the time of the rising clock transi- tion), a valid input si gnal is still required to complete the transition and to reach v ih ( ac )/ v il ( ac ) (see figure 17 on page 42 for input signal requirements). for slew rates which fall between the values listed in table 56 on page 78 and table 57 on page 79, the derating values may be obtained by linear interpolation. setup ( t is) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of v ref ( dc ) and the first crossing of v ih ( ac ) min. setup ( t is) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ref ( dc ) and the first crossing of v il ( ac ) max. if the actual signal is always earlier than the nominal slew rate line between the shaded ?v ref ( dc )-to-ac region,? use the nominal slew rate for derating value (see figure 35 on page 80). if the actual signal is later than the nominal slew rate line anywhere between the shaded ?v ref ( dc )-to-ac region,? the slew rate of a tangent line to the actual signal from the ac level to the dc level is used for derating value (see figure 37 on page 82). hold ( t ih) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of v il ( dc ) max and the first crossing of v ref ( dc ). hold ( t ih) nominal slew rate for a falling signal is defined as the slew rate be tween the last crossing of v ih ( dc ) min and the first crossing of v ref ( dc ). if the actual signal is always later than the nominal slew rate line be tween the shaded ?dc-to-v ref ( dc ) region,? use the nominal slew rate for derating value (see figure 36 on page 81). if the actual signal is earlier than the nominal slew rate line anywhere between the shaded ?dc-to-v ref ( dc ) region,? the slew rate of a tangent line to the actual signal from the dc level to the v ref ( dc ) level is used for derating value (see figure 38 on page 83). table 54: command and address setup and hold va lues referenced at 1 v/ns ? ac/dc-based symbol ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 units reference t is (base) 200 125 65 45 ps v ih ( ac )/v il ( ac ) t ih (base) 275 200 140 120 ps v ih ( dc )/v il ( dc ) t is (base): ac150 n/a n/a 190 170 ps v ih ( ac )/v il ( ac )
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_3.fm - rev. d 8/1/08 en 78 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram speed bin tables table 55: ddr3-800, ddr3-1066, ddr3-1333, and ddr3-1600 derating values for t is/ t ih ? ac/dc- based ac175 threshold t is, t ih derating (ps) ? ac/dc-based ac175 threshold: v ih ( ac ) = v ref ( dc ) + 175mv, v il ( ac ) = v ref ( dc ) - 175mv cmd/ addr slew rate v/ns ck, ck# differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns t is t ih t is t ih t is t ih t is t ih t is t ih t ih t ih t is t ih t is t ih 2.0 88 50 88 50 88 50 96 58 104 66 112 74 120 84 128 100 1.5 59345934593467427550835891689984 1.0 000000881616242432344050 0.9 ?2?4?2?4?2?4 6 4 1412222030303846 0.8 ?6 ?10 ?6 ?10 ?6 ?10 2 ?2 10 6 18 14 26 24 34 40 0.7 ?11 ?16 ?11 ?16 ?11 ?16 ?3 ?8 5 0 13 8 21 18 29 34 0.6 ?17 ?26 ?17 ?26 ?17 ?26 ?9 ?18 ?1 ?10 7 ?2 15 8 23 24 0.5 ?35 ?40 ?35 ?40 ?35 ?40 ?27 ?32 ?19 ?24 ?11 ?16 ?2 ?6 5 10 0.4 ?62 ?60 ?62 ?60 ?62 ?60 ?54 ?52 ?46 ?44 ?38 ?36 ?30 ?26 ?22 ?10 table 56: ddr3-1333 and ddr3-1600 derating values for t is/ t ih ? ac/dc-based ac150 threshold t is, t ih derating (ps) ? ac/dc-based ac150 threshold: v ih ( ac ) = v ref ( dc ) + 150mv, v il ( ac ) = v ref ( dc ) - 150mv cmd/ addr slew rate v/ns ck, ck# differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns t is t ih t is t ih t is t ih t is t ih t is t ih t ih t ih t is t ih t is t ih 2.0 75507550755083589166997410784115100 1.5 50345034503458426650745882689084 1.0 000000881616242432344050 0.9 0 ?4 0 ?4 0 ?4 8 4 16 12 24 20 32 30 40 46 0.8 0 ?10 0 ?10 0 ?10 8 ?2 16 6 241432244040 0.7 0 ?16 0 ?16 0 ?16 8 ?8 16 0 24 8 32 18 40 34 0.6 ?1 ?26 ?1 ?26 ?1 ?26 7 ?18 15 ?10 23 ?2 31 8 39 24 0.5 ?10 ?40 ?10 ?40 ?10 ?40 ?2 ?32 6 ?24 14 ?16 22 ?6 30 10 0.4 ?25 ?60 ?25 ?60 ?25 ?60 ?17 ?52 ?9 ?44 ?1 ?36 7 ?26 15 ?10
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_3.fm - rev. d 8/1/08 en 79 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram speed bin tables table 57: minimum required time t vac above v ih ( ac ) for valid transition below v il ( ac ) slew rate (v/ns) t vac at 175mv (ps) t vac at 150mv (ps) >2.0 75 175 2.0 57 170 1.5 50 167 1.0 38 163 0.9 34 162 0.8 29 161 0.7 22 159 0.6 13 155 0.5 0 150 <0.5 0 150
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_3.fm - rev. d 8/1/08 en 80 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram speed bin tables figure 35: nominal slew rate and t vac for t is (command and address ? clock) notes: 1. both the clock and the strobe are drawn on different time scales. v ss s etup slew rate risin g si g nal s etup slew rate fallin g si g nal tf tr == v dd q v ih ( a c ) min v ih ( d c ) min v ref ( d c ) v il ( d c ) max v il ( d c ) max nominal slew rate v ref to a c re g ion t va c t va c dq s dq s # c k# c k t i s t ih t i s t ih nominal slew rate v ref to a c re g ion v ref ( d c ) - v il ( a c ) max tf v ih ( a c ) min - v ref ( d c ) tr
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_3.fm - rev. d 8/1/08 en 81 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram speed bin tables figure 36: nominal slew rate for t ih (command and address ? clock) notes: 1. both the clock and the strobe are drawn on different time scales. v ss hol d slew rate fallin g si g nal hol d slew rate risin g si g nal tr tf = = v dd q v ih ( a c ) min v ih ( d c ) min v ref ( d c ) v il ( d c ) max v il ( a c ) max nominal slew rate d c to v ref re g ion dq s dq s # c k# c k t i s t ih t i s t ih d c to v ref re g ion nominal slew rate v ref ( d c ) - v il ( d c ) max tr v ih ( d c ) min - v ref ( d c ) tf
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_3.fm - rev. d 8/1/08 en 82 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram speed bin tables figure 37: tangent line for t is (command and address ? clock) notes: 1. both the clock and the strobe are drawn on different time scales. v ss s etup slew rate risin g si g nal s etup slew rate fallin g si g nal tf tr = = v dd q v ih ( a c ) min v ih ( d c ) min v ref ( d c ) v il ( d c ) max v il ( a c ) max tan g ent line v ref to a c re g ion nominal line t va c t va c dq s dq s # c k# c k t i s t ih t i s t ih v ref to a c re g ion tan g ent line nominal line tan g ent line (v ih [ d c ] min - v ref [ d c ]) tr tan g ent line (v ref [ d c ] - v il [ a c ] max) tf
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_3.fm - rev. d 8/1/08 en 83 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram speed bin tables figure 38: tangent line for t ih (command and address ? clock) notes: 1. both the clock and the strobe are drawn on different time scales. v ss hol d slew rate fallin g si g nal tr = v dd q v ih ( a c ) min v ih ( d c ) min v ref ( d c ) v il ( d c ) max v il ( a c ) max tan g ent line d c to v ref re g ion hol d slew rate risin g si g nal = dq s dq s # c k# c k t i s t ih t i s t ih d c to v ref re g ion tan g ent line nominal line nominal line tr tan g ent line (v ref [ d c ] - v il [ d c ] max) tr tan g ent line (v ih [ d c ] min - v ref [ d c ]) tf
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_3.fm - rev. d 8/1/08 en 84 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram speed bin tables data setup, hold, and derating the total t ds (setup time) and t dh (hold time) required is calculated by adding the data sheet t ds (base) and t dh (base) values (see table 58; values come from table 53 on page 67) to the t ds and t dh derating values (see table 59 on page 85), respectively. example: t ds (total setup time) = t ds (base) + t ds. for a valid transition, the input signal has to remain above/below v ih ( ac )/v il ( ac ) for some time t vac (see table 61 on page 86). although the total setup time for slow slew rates might be negative (for example, a valid input signal will not have reached v ih [ ac ]/v il [ ac ]) at the time of the rising clock transi- tion), a valid input signal is still required to complete the transition and to reach v ih / v il ( ac ). for slew rates which fall between the values listed in table 59 on page 85, the derating values may obtained by linear interpolation. setup ( t ds) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of v ref ( dc ) and the first crossing of v ih ( ac ) min. setup ( t ds) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ref ( dc ) and the first crossing of v il ( ac ) max. if the actual signal is always earlier than the nominal slew rate line between the shaded ?v ref ( dc )-to-ac region,? use the nominal slew rate for derating value (see figure 39 on page 87). if the actual signal is later than the nominal slew rate line anywhere between the shaded ?v ref ( dc )-to-ac region,? the slew rate of a tangent line to the actual signal from the ac level to the dc level is used for derating value (see figure 41 on page 89). hold ( t dh) nominal slew rate for a rising signal is defined as the sl ew rate between the last crossing of v il ( dc ) max and the first crossing of v ref ( dc ). hold ( t dh) nominal slew rate for a falling signal is defined as the slew rate be tween the last crossing of v ih ( dc ) min and the first crossing of v ref ( dc ). if the actual signal is always later than the nominal slew rate line be tween the shaded ?dc-to-v ref ( dc ) region,? use the nominal slew rate for derating value (see figure 40 on page 88). if the actual signal is earlier than the nominal slew rate line anywhere between the shaded ?dc-to-v ref ( dc ) region,? the slew rate of a tangent line to the actual signal from the ?dc-to-v ref ( dc ) region? is used for derating value (see figure 42 on page 90). table 58: data setup and hold values at 1 v/ns (dqs, dqs# at 2 v/ns ) ? ac/dc-based symbol ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 units reference t ds ac175 (base) 75 25 ? ? ps v ih ( ac )/v il ( ac ) t dh ac175 (base) 150 100 ? ? ps v ih ( dc )/v il ( dc ) t ds ac150 (base) ? ? 30 10 ps v ih ( ac )/v il ( ac ) t dh ac150 (base) ? ? 65 45 ps v ih ( dc )/v il ( dc )
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_3.fm - rev. d 8/1/08 en 85 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram speed bin tables table 59: ddr3-800, ddr3-1066, ddr3-1333, and ddr3-1600 derating values for t ds/ t dh ? ac/dc- based ac175 threshold; shaded cells indicate slew rate combinat ions not supported t ds, t dh derating (ps) ? ac/dc-based dq slew rate v/ns dqs, dqs# differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh 2.0 885088508850 1.5 5934593459346742 1.0 000000881616 0.9 ?2 ?4 ?2 ?4 6 4 14 12 22 20 0.8 ?6 ?10 2 ?2 10 6 18 14 26 24 0.7 ?3 ?8 5 0 13 8 21182934 0.6 ?1 ?10 7 ?2 15 8 23 24 0.5 ?11 ?16 ?2 ?6 5 10 0.4 ?30 ?26 ?22 ?10 table 60: ddr3-1333and ddr3-1600 derating values for t ds/ t dh ? ac/dc-based ac150 threshold; shaded cells indicate slew rate combinat ions not supported t ds, t dh derating (ps) ? ac/dc-based cmd/ addr slew rate v/ns dqs, dqs# differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns t is t ih t is t ih t is t ih t is t ih t is t ih t ih t ih t is t ih t is t ih 2.0 755075507550 1.5 5034503450345842 1.0 000000881616 0.9 0 ?4 0 ?4 8 4 16 12 24 20 0.8 0?108?216624143224 0.7 8 ?8 16 0 24 8 32 18 40 34 0.6 15 ?10 23 ?2 31 8 39 24 0.5 14?1622?63010 0.4 7 ?26 15 ?10
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_3.fm - rev. d 8/1/08 en 86 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram speed bin tables table 61: required time t vac above v ih ( ac ) (below v il [ ac ]) for valid transition slew rate (v/ns) t vac at 175mv (ps) t vac at 150mv (ps) min min >2.0 75 175 2.0 57 170 1.5 50 167 1.0 38 163 0.9 34 162 0.8 29 161 0.7 22 159 0.6 13 155 0.5 0 150 <0.5 0 150
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_3.fm - rev. d 8/1/08 en 87 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram speed bin tables figure 39: nominal slew rate and t vac for t ds (dq ? strobe) notes: 1. both the clock and the strobe are drawn on different time scales. v ss s etup slew rate risin g si g nal s etup slew rate fallin g si g nal tf tr = = v dd q v ih ( a c ) min v ih ( d c ) min v ref ( d c ) v il ( d c ) max v il ( a c ) max nominal slew rate v ref to a c re g ion t va c t va c t dh t d s dq s dq s # t dh t d s c k# c k v ref to a c re g ion nominal slew rate v ih ( a c ) min - v ref ( d c ) tr v ref ( d c ) - v il ( a c ) max tf
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_3.fm - rev. d 8/1/08 en 88 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram speed bin tables figure 40: nominal slew rate for t dh (dq ? strobe) notes: 1. both the clock and the strobe are drawn on different time scales. v ss hol d slew rate fallin g si g nal hol d slew rate risin g si g nal tr tf == v dd q v ih ( a c ) min v ih ( d c ) min v ref ( d c ) v il ( d c ) max v il ( a c ) max nominal slew rate d c to v ref re g ion t dh t d s dq s dq s # t dh t d s c k# c k d c to v ref re g ion nominal slew rate v ref ( d c ) - v il ( d c ) max tr v ih ( d c ) min - v ref ( d c ) tf
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_3.fm - rev. d 8/1/08 en 89 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram speed bin tables figure 41: tangent line for t ds (dq ? strobe) notes: 1. both the clock and the strobe are drawn on different time scales. v ss s etup slew rate risin g si g nal s etup slew rate fallin g si g nal tf tr = = v dd q v ih ( a c ) min v ih ( d c ) min v ref ( d c ) v il ( d c ) max v il ( a c ) max tan g ent line v ref to a c re g ion nominal line t va c t va c t dh t d s dq s dq s # t dh t d s c k# c k v ref to a c re g ion tan g ent line nominal line tr tan g ent line (v ref [ d c ] - v il [ a c ] max) tf tan g ent line (v ih [ a c ] min - v ref [ d c ])
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_3.fm - rev. d 8/1/08 en 90 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram speed bin tables figure 42: tangent line for t dh (dq ? strobe) notes: 1. both the clock and the strobe are drawn on different time scales. v ss hol d slew rate fallin g si g nal tf tr = v dd q v ih ( a c ) min v ih ( d c ) min v ref ( d c ) v il ( d c ) max v il ( a c ) max tan g ent line d c to v ref re g ion hol d slew rate risin g si g nal = dq s dq s # c k# c k d c to v ref re g ion tan g ent line nominal line nominal line tan g ent line (v ih [ d c ] min - v ref [ d c ]) tf tan g ent line (v ref [ d c ] - v il [ d c ] max) tr t d s t dh t d s t dh
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 91 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram commands commands truth tables notes: 1. commands are defined by states of cs#, ras#, cas#, we#, and cke at the rising edge of the clock. the msb of ba, ra, and ca are de vice-density and configuration-dependent. 2. reset# is low enabled and used only for asynch ronous reset. thus, reset# must be held high during any normal operation. 3. the state of odt does not affect the states described in this table. table 62: truth table ? command notes 1?5 apply to the entire table function symbol cke cs# ras# cas# we# ba [2:0] a n a12 a10 a[11, 9:0] notes prev cycle next cycle mode register set mrs h h l l l l ba op code refresh ref h h l l l h v v v v v self refresh entry sre h l l l l h v v v v v 6 self refresh exit srx l h h v v v v v v v v 6, 7 lh hh single-bank prechar ge pre h h l l h l ba v v l v precharge all banks prea h h l l h l v v v h v bank activate act h h l l h h ba row address (ra) write bl8mrs, bc4mrs wr h h l h l l ba rfu v l ca 8 bc4otf wrs4 h h l h l l ba rfu l l ca 8 bl8otf wrs8 h h l h l l ba rfu h l ca 8 write with auto precharge bl8mrs, bc4mrs wrap h h l h l l ba rfu v h ca 8 bc4otf wraps4 h h l h l l ba rfu l h ca 8 bl8otf wraps8 h h l h l l ba rfu h h ca 8 read bl8mrs, bc4mrs rd h h l h l h ba rfu v l ca 8 bc4otf rds4 h h l h l h ba rfu l l ca 8 bl8otf rds8 h h l h l h ba rfu h l ca 8 read with auto precharge bl8mrs, bc4mrs rdap h h l h l h ba rfu v h ca 8 bc4otf rdaps4 h h l h l h ba rfu l h ca 8 bl8otf rdaps8 h h l h l h ba rfu h h ca 8 no operation nop h h l h h h v v v v v 9 device deselected des h h h x x x x x x x x 10 power-down entry pde h l l h h h v v v v v 6 hv v v power-down exit pdx l h l h h h v v v v v 6, 11 hv v v zq calibration long zqcl h h l h h l x x x h x 12 zq calibration short zqcs h h l h h l x x x l x
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 92 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram commands 4. operations apply to the bank defined by the bank address. for mrs, ba selects one of four mode registers. 5. ?v? means ?h? or ?l? (a defined logi c level), and ?x? means ?don?t care.? 6. see table 63 for additional in formation on ck e transition. 7. self refresh exit is asynchronous. 8. burst reads or writes cannot be terminated or interrupted. mrs (fix ed) and otf bl/bc are defined in mr0. 9. the purpose of the nop command is to prev ent the dram from registering any unwanted commands. a nop will not terminate an operation that is executing. 10. the des and nop commands perform similarly. 11. the power-down mode does not perform any refresh operations. 12. zq calibration long is used for either zq init (first zqcl command during initialization) or zq oper (zqcl command after initialization). notes: 1. all states and se q uences not shown are ille gal or reserved unless ex plicitly described else- where in this document. 2. t cke (min) means cke must be registered at mult iple consecutive positive clock edges. cke must remain at the valid input level the entire time it takes to achieve the re q uired number of registration clocks. thus, after any cke transiti on, cke may not transition from its valid level during the time period of t is + t cke (min) + t ih. 3. current state = the state of the dr am immediately prior to clock edge n . 4. cke ( n ) is the logic state of cke at clock edge n ; cke ( n - 1) was the state of cke at the pre- vious clock edge. 5. command is the command registered at the clock edge (must be a legal command as defined in table 62 on page 91). action is a result of command. odt does not affect the states described in this table and is not listed. 6. idle state = all banks are closed, no data burst s are in progress, cke is high, and all timings from previous operations are sati sfied. all self refresh exit and power-down exit parameters are also satisfied. deselect (des) the des command (cs# high) prevents new commands from being executed by the dram. operations already in progress are not affected. table 63: truth table ? cke notes 1?2 apply to the entire table; see table 62 on page 91 for additional command details current state 3 cke command 5 (ras#, cas#, we#, cs#) action 5 notes previous cycle 4 ( n -1) present cycle 4 ( n ) power-down l l ?don?t care? maintain power-down l h des or nop power-down exit self refresh l l ?don?t care? maintain self refresh l h des or nop self refresh exit bank(s) active h l des or no p active power-down entry reading h l des or nop power-down entry writing h l des or nop power-down entry precharging h l des or nop power-down entry refreshing h l des or nop precharge power-down entry all banks idle h l des or nop p recharge power-down entry 6 h l refresh self refresh
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 93 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram commands no operation (nop) the nop command (cs# low) prevents unwanted commands from being registered during idle or wait states. operations already in progress are not affected. zq calibration zq calibration long (zqcl) the zqcl command is used to perform the in itial calibration during a power-up initial- ization and reset sequence (see figure 51 on page 107). this command may be issued at any time by the controller depending on the system environment. the zqcl command triggers the calibration engine inside the dr am. after calibration is achieved, the cali- brated values are transferred from the calibration engine to the dram i/o, which are reflected as updated r on and odt values. the dram is allowed a timing window defined by either t zq init or t zq oper to perform the full calibration and transfer of values. wh en zqcl is issued during the initialization sequence, the timing parameter t zq init must be satisfied. when initialization is complete, subsequent zqcl commands require the timing parameter t zq oper to be satisfied. zq calibration short (zqcs) the zqcs command is used to perform peri odic calibrations to account for small voltage and temperature variations. the shorte r timing window is provided to perform the reduced calibration and transfer of values as defined by timing parameter t zqcs. a zqcs command can effectively correct a minimum of 0.5 percent r on and r tt impedance error within 64 clock cycles, assuming the maximum sensitivities specified in tabl e 40 on pag e 56 and tab le 4 1 on pa ge 5 7. activate the activate command is used to open (or activate) a row in a particular bank for a subsequent access. the value on the ba[2:0] inputs selects the bank, and the address provided on inputs a[ n :0] selects the row. this row rema ins open (or active) for accesses until a precharge command is issued to that bank. a precharge command must be issued before opening a different row in the same bank. read the read command is used to initiate a burst read access to an active row. the address provided on inputs a[2:0] selects the starti ng column address depending on the burst length and burst type select ed (see table 68 on page 111 for additional information). the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the read burst. if auto precharge is not selected, the row will remain open for subsequent accesses. the value on input a12 (if enabled in the mode register) when the read command is issued determines whether bc4 (chop) or bl8 is used. after a read command is issued, the read burst may no t be interrupted. a summary of read commands is shown in table 64 on page 94.
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 94 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram commands write the write command is used to initiate a burst write access to an active row. the value on the ba[2:0] inputs selects the bank. the value on input a10 determines whether or not auto precharge is used. the value on input a12 (if enabled in the mr) when the write command is issued determines whether bc4 (chop) or bl8 is used. the write command summary is shown in table 65. input data appearing on the dq is written to the memory array subject to the dm input logic level appearing coincident with the data. if a given dm signal is registered low, the corresponding data will be written to memory. if the dm signal is registered high, the corresponding data inputs will be ignored and a write will not be executed to that byte/column location. precharge the precharge command is used to deactivate the open row in a particular bank or in all banks. the bank(s) are av ailable for a subsequent row access a specified time ( t rp) after the precharge command is issued, except in the case of concurrent auto precharge. a read or write command to a di fferent bank is allowed during concurrent auto precharge as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters . input a10 determines whether one or all banks are precharged. in the case where only one bank is precharged, inputs ba[2:0] select the bank; otherwise, ba[2:0] are tr eated as ?don?t care.? after a bank is precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. a pr echarge command is treated as a nop if table 64: read command summary function symbol cke cs# ras# cas# we# ba [3:0] a n a12 a10 a[11, 9:0] previous cycle next cycle read bl8mrs, bc4mrs rd h l h l h ba rfu v l ca bc4otf rds4 h l h l h ba rfu l l ca bl8otf rds8 h l h l h ba rfu h l ca read with auto precharge bl8mrs, bc4mrs rdap h l h l h ba rfu v h ca bc4otf rdaps4 h l h l h ba rfu l h ca bl8otf rdaps8 h l h l h ba rfu h h ca table 65: write command summary function symbol cke cs# ras# cas# we# ba [3:0] a n a12 a10 a[11, 9:0] prev cycle next cycle write bl8mrs, bc4mrs wr h l h l l ba rfu v l ca bc4otf wrs4 h l h l l ba rfu l l ca bl8otf wrs8 h l h l l ba rfu h l ca write with auto precharge bl8mrs, bc4mrs wrap h l h l l ba rfu v h ca bc4otf wraps4 h l h l l ba rfu l h ca bl8otf wraps8 h l h l l ba rfu h h ca
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 95 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram commands there is no open row in that bank (idle state) or if the previously open row is already in the process of precharging. however, the pr echarge period is determined by the last precharge command issued to the bank. refresh refresh is used during normal operation of the dram and is analogous to cas#- before-ras# (cbr) refresh or auto refresh. this command is nonpersistent, so it must be issued each time a refresh is required. the addressing is generated by the internal refresh controller. this makes the address bits a ?don?t care? during a refresh command. the dram requires refresh cycles at an av erage interval of 7.8s (maximum when t c 85c or 3.9s max when t c 95c). to allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. a maximum of eight refresh commands can be posted to any given dram, meaning that the maximum absolute interval be tween any refresh command and the next refresh command is nine times the maximum average interval refresh rate. the refresh period begins when the refresh command is registered and ends t rfc (min) later. figure 43: refresh mode notes: 1. nop commands are shown for ease of illus tration; other valid commands may be possible at these times. cke must be active during the precharge, activa te, and refresh com- mands, but may be inactive at other time s (see "power-down mode" on page 151). 2. the second refresh is not re q uired but depicts two back-to-back refresh commands. 3. ?don?t care? if a10 is high at this point; however, a10 must be high if more than one bank is active (must precharge all active banks). 4. for operations shown, dm, dq, and dqs signals are all ?don?t care?/high-z. nop 1 nop 1 nop 1 pre ra bank(s) 3 ba ref nop 1 ref 2 nop 1 act nop 1 one bank all banks t ck t ch t cl ra t rfc 2 t rp t rfc (min) t0 t1 t2 t3 t4 ta0 tb0 ta1 tb1 tb2 don?t care indicates a break in time scale valid 1 valid 1 valid 1 ck ck# command cke address a10 ba[2:0] dq 4 dm 4 dqs, dqs# 4
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 96 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram commands self refresh the self refresh command is used to retain data in the dram, even if the rest of the system is powered down. when in the self refresh mode, the dram retains data without external clocking. the self refresh mode is also a convenient method used to enable/ disable the dll (see ?dll disable mode? on page 96) as well as to change the clock frequency within the allowed synchronous operating range (see ?input clock frequency change? on page 99). all power supply inputs (including v ref ca and v ref dq) must be maintained at valid levels upon entry/ exit and during self refresh operation. dll disable mode if the dll is disabled by the mode register (mr1[0] can be switched during initialization or later), the dram is targeted, but not guar anteed, to operate similarly to the normal mode with a few notable exceptions: ? the dram supports only one value of cas latency (cl = 6) and one value of cas write latency (cwl = 6). ? dll disable mode affects the read data clock-to-data strobe relationship ( t dqsck), but not the read data-to-data strobe relationship ( t dqsq, t qh). special attention is needed to line the read data up with the controller time domain when the dll is disabled. ? in normal operation (dll on), t dqsck starts from the rising clock edge al + cl cycles after the read command. in dll disable mode, t dqsck starts al + cl - 1 cycles after the read command. additionally, with the dll disabled, the value of t dqsck could be larger than t ck. the odt feature is not supported during dll disable mode (including dynamic odt). the odt resistors must be disabled by cont inuously registering the odt ball low by programming r tt _ nom mr1[9, 6, 2] and r tt _ wr mr2[10, 9] to ?0? while in the dll disable mode. specific steps must be followed to switch between the dll enable and dll disable modes due to a gap in the allowed clock rates between the two modes ( t ck [avg] max and t ck [dll disable] min, respectively). the only time the clock is allowed to cross this clock rate gap is during self refresh mode. thus, the required procedure for switching from the dll enable mode to the dll disable mode is to change frequency during self refresh (see figure 44 on page 97): 1. starting from the idle state (all banks are precharged, all timings are fulfilled, odt is turned off, and r tt _ nom and r tt _ wr are high-z), set mr1[0] to ?1? to disable the dll. 2. enter self refresh mode after t mod has been satisfied. 3. after t cksre is satisfied, change the frequency to the desired clock rate. 4. self refresh may be exited when the clock is stable with the new frequency for t cksrx. after t xs is satisfied, update the mode registers with appropriate values. 5. the dram will be ready for its next command in the dll disable mode after the greater of t mrd or t mod has been satisfied. a zqcl command should be issued with appropriate timing s met as well.
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 97 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram commands figure 44: dll enable mode to dll disable mode notes: 1. any valid command. 2. disable dll by setting mr1[0] to ?1.? 3. enter self refresh. 4. exit self refresh. 5. update the mode registers with the dll disable parameters setting. 6. starting with the idle state, r tt is in the high-z state. 7. change fre q uency. 8. clock must be stable t cksrx. 9. static low in case r tt _ nom or r tt _ wr is enabled; otherwise, static low or high. a similar procedure is required for switching from the dll disable mode back to the dll enable mode. this also requires changing the frequency during self refresh mode (see figure 45 on page 98). 1. starting from the idle state (all banks are precharged, all timings are fulfilled, odt is turned off, and r tt _ nom and r tt _ wr are high-z), enter self refresh mode. 2. after t cksre is satisfied, change the frequency to the new clock rate. 3. self refresh may be exited when the clock is stable with the new frequency for t cksrx. after t xs is satisfied, update the mode registers with the appropriate values. at a min- imum, set mr1[0] to ?0? to enable the dll. wait t mrd, then set mr0[8] to ?1? to enable dll reset. 4. after another t mrd delay is satisfied, then update the remaining mode registers with the appropriate values. 5. the dram will be ready for its next command in the dll enable mode after the greater of t mrd or t mod has been satisfied. however, before applying any command or function requiring a locked dll, a delay of t dllk after dll reset must be satis- fied. a zqcl command should be issued wi th the appropriate ti mings met as well. c omman d t0 t1 ta0 ta1 t b 0t c 0 7 6 t d 0t d 1 te0 te1 tf0 c k c k# odt 9 vali d 1 don ? t c are vali d 1 s re 3 nop mr s 2 nop s rx 4 mr s 5 vali d 1 nop nop in d i c ates a break in time sc ale t mod t c k s re t mod t x s t c ke s r c ke t c k s rx 8
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 98 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram commands figure 45: dll disable mode to dll enable mode notes: 1. enter self refresh. 2. exit self refresh. 3. wait t xs, then set mr1[0] to ?0? to enable dll. 4. wait t mrd, then set mr0[8] to ?1? to begin dll reset. 5. wait t mrd, update registers (cl, cwl, an d write recovery may be necessary). 6. wait t mod, any valid command. 7. starting with the idle state. 8. change fre q uency. 9. clock must be stable at least t cksrx. 10. static low in case r tt _ nom or r tt _ wr is enabled; otherwise, static low or high. the clock frequency range for the dll disable mode is specified by the parameter t ck dll _ dis . due to latency counter and timing restrictions, only cl = 6 and cwl = 6 are supported. dll disable mode will affect the read data clock to data strobe relationship ( t dqsck) but not the data strobe to data relationship ( t dqsq, t qh). special attention is needed to line up read data to the controller time domain. compared to the dll on mode where t dqsck starts from the rising clock edge al + cl cycles after the read command, the dll disable mode t dqsck starts al + cl - 1 cycles after the read command (see figure 46 on page 99). write operations function similarly between the dll enable and dll disable modes; however, odt functionality is not allowed with dll disable mode. c ke t0 ta0 ta1 t b 0t c 0t c 1t d 0 te0 tf0 t g 0 c k c k# odt 10 s re 1 nop c omman d nop s rx 2 mr s 3 mr s 4 mr s 5 vali d 6 vali d don ? t c are 78 in d i c ates a break in time sc ale t c k s re t c k s rx 9 t x s t mrd t mrd t c ke s r odtl off + 1 t c k th0 t dllk
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 99 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram commands figure 46: dll disable t dqsck timing input clock frequency change when the ddr3 sdram is initialized, it requires the clock to be stable during most normal states of operation. this means that after the clock frequency has been set to the stable state, the clock period is not allowed to deviate except what is allowed for by the clock jitter and spread spectrum clocking (ssc) specifications. the input clock frequency can be changed from one stable clock rate to another under two conditions: self refresh mode and precharge power-down mode. outside of these two modes, it is illegal to change the clock frequency. for the self refresh mode condi- tion, when the ddr3 sdram has been successfully placed into self refresh mode and t cksre has been satisfied, the state of the clock becomes a ?don?t care.? when the clock becomes a ?don?t care,? changing the clock frequency is permissible, provided the new clock frequency is stable prior to t cksrx. when entering and exiting self refresh mode for the sole purpose of changing the clock frequency, the self refresh entry and exit spec- ifications must still be met. the precharge power-down mode condition is when the ddr3 sdram is in precharge power-down mode (either fast exit mode or slow exit mode). either odt must be at a logic low or r tt _ nom and r tt _ wr must be disabled via mr1 and mr2. this ensures r tt _ nom and r tt _ wr are in an off state prior to entering precharge power-down mode, and cke must be at a logic low. a minimum of t cksre must occur after cke goes low before the clock frequency can change. the ddr3 sdram input clock frequency is allowed to change only within the minimum and maximum operating frequency specified for the particular speed grade ( t ck [avg] min to t ck [avg] max). during the input clock frequency change, cke must be held at a stable low level. when the input clock frequency is changed, a stable clock must be provided to the dram t cksrx before precharge power-down may be exited. after precharge power-down is exited and t xp has table 66: read electrical chara cteristics, dll disable mode parameter symbol min max units access window of dqs from ck, ck# t dqsck ( dll _ dis )110ns t0 t1 t2 t3 t4 t5 t 6 t7 t8 t9 t10 don ? t c are transitionin g data vali d nop read nop nop nop nop nop nop nop nop nop c k c k# c omman d a dd ress di b + 3 di b + 2 di b + 1 di b di b + 7 di b + 6 di b + 5 di b + 4 dq bl8 dll on dq s , dq s # dll on dq bl8 dll d isa b le dq s , dq s # dll off dq bl8 dll d isa b le dq s , dq s # dll off rl = al + c l = 6 ( c l = 6 , al = 0) c l = 6 di b + 3 di b + 2 di b + 1 di b di b + 7 di b + 6 di b + 5 di b + 4 di b + 3 di b + 2 di b + 1 di b di b + 7 di b + 6 di b + 5 di b + 4 t dq sc k ( dll _ di s ) min t dq sc k ( dll _ di s ) max rl (dll d isa b le) = al + ( c l - 1) = 5
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 100 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram commands been satisfied, the dll must be reset via the mrs. depending on the new clock frequency, additional mrs commands may need to be issued. during the dll lock time, r tt _ nom and r tt _ wr must remain in an off state. after the dll lock time, the dram is ready to operate with a new clock frequency. this process is depicted in figure 47. figure 47: change frequency during precharge power-down notes: 1. applicable fo r both slow-exit and fast-exi t precharge power-down modes. 2. t aofpd and t aof must be satisfied and outputs high-z prior to t1 (see "on-die termina- tion (odt)" on page 160 for exact re q uirements). 3. if the r tt _ nom feature was enabled in the mode re gister prior to entering precharge power-down mode, the odt si gnal must be continuously registered low ensuring r tt is in an off state. if the r tt _ nom feature was disabled in the mode register prior to entering pre- charge power-down mode, r tt will remain in the off state. the odt signal can be regis- tered either low or high in this case. ck ck# command nop nop nop address cke dq dm dqs, dqs# nop t ck enter precharge power-down mode exit precharge power-down mode t0 t1 ta0 tc0 tb0 t2 don?t care t cke t xp mrs dll reset valid valid nop t ch t ih t is t cl tc1 td0 te1 td1 t cksre t ch b t cl b t ck b t ch b t cl b t ck b t ch b t cl b t ck b t cpded odt nop te0 previous clock fre q uency new clock fre q uency fre q uency change indicates a break in time scale t ih t is t ih t is t dllk t aofpd/ t aof t cksrx high-z high-z
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 101 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram commands write leveling for better signal integrity, ddr3 sdram memory modules adopted fly-by topology for the commands, addresses, control signals, and clocks. write leveling is a scheme for the memory controller to adjust or deskew the dqs strobe (dqs, dqs#) to ck relationship at the dram with a simple feedback featur e provided by the dram. write leveling is generally used as part of the initialization process, if required. for normal dram opera- tion, this feature must be disabled. this is the only dram operation where the dqs functions as an input (to capture the incoming clock) and the dq function as outputs (to report the state of the clock). note that nonstandard odt schemes are required. the memory controller using the write leveling procedure must have adjustable delay settings on its dqs strobe to align the rising edge of dqs to the clock at the dram pins. this is accomplished when the dram asynchronously feeds back the ck status via the dq bus and samples with the rising edge of dqs. the controller repeatedly delays the dqs strobe until a ck transition from ?0? to ?1? is detected. the dqs delay established through this procedure helps ensure t dqss, t dss, and t dsh specifications in systems that use fly-by topology by deskewing the tr ace length mismatch. a conceptual timing of this procedure is shown in figure 48. figure 48: write leveling concept ck ck# source differential dqs differential dqs differential dqs dq dq ck ck# destination destination push dqs to capture 0?1 transition t0 t1 t2 t3 t4 t5 t6 t7 t0 t1 t2 t3 t4 t5 t6 tn ck ck# t0 t1 t2 t3 t4 t5 t6 tn don?t care 1 1 0 0
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 102 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram commands when write leveling is enabled, the rising edge of dqs samples ck, and the prime dq outputs the sampled ck?s status. the prime dq for a x4 or x8 configuration is dq0 with all other dq (dq[7:1]) driving low. the prime dq for a x16 configuration is dq0 for the lower byte and dq8 for the upper byte. it outputs the status of ck sampled by ldqs and udqs. all other dq (dq[7:1], dq[15:9]) contin ue to drive low. two prime dq on a x16 enable each byte lane to be leveled independently. the write leveling mode register interacts with other mode registers to correctly configure the write leveling functionality. besides using mr1[7] to disable/enable write leveling, mr1[12] must be used to enable/disable the output buffers. the odt value, burst length, and so forth need to be selected as well. this interaction is shown in table 67. it should also be noted that when the outputs are enabled during write leveling mode, the dqs buffers are set as inputs, and the dq are set as outputs. additionally, during write leveling mode, only the dqs strobe terminations are activated and deacti- vated via the odt ball. the dq remain disabl ed and are not affected by the odt ball (see table 67). notes: 1. expected usage if used during write leve ling: case 1 may be used when dram are on a dual-rank module and on the rank not being levelized or on any rank of a module not being levelized on a multislott ed system. case 2 may be used when dram are on any rank of a module not being levelized on a multislotte d system. case 3 is ge nerally not used. case 4 is generally used when dram are on the rank that is being leveled. 2. since the dram dqs is not being driven (m r1[12] = 1), dqs ignores the input strobe, and all r tt _ nom values are allowed. this simula tes a normal standby state to dqs. 3. since the dram dqs is being driven (mr1[12] = 0), dqs captures th e input strobe, and only some r tt _ nom values are allowed. this simula tes a normal write state to dqs. table 67: write leveling matrix note 1 applies to the entire table mr1[7] mr1[12] mr1[3, 6, 9] dram odt ball dram r tt _ nom dram state case notes write leveling output buffers r tt _ nom value dqs dq disabled see normal operations write leveling not enabled 0 enabled (1) disabled (1) n/a low off off dqs not receiving: not terminated prime dq high-z: not terminated other dq high-z: not terminated 12 20 , 30 , 40 , 60 , or 120 high on dqs not receiving: terminated by r tt prime dq high-z: not terminated other dq high-z: not terminated 2 enabled (0) n/a low off dqs receiving: not terminated prime dq driving ck state: not terminated other dq driving low: not terminated 33 40 , 60 , or 120 high on dqs receiving: terminated by r tt prime dq driving ck state: not terminated other dq driving low: not terminated 4
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 103 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram commands write leveling procedure a memory controller initiates the dram write leveling mode by setting mr1[7] to a ?1,? assuming the other programable features (m r0, mr1, mr2, and mr3) are first set and the dll is fully reset and locked. the dq ball s enter the write leveling mode going from a high-z state to an undefined driving state, so the dq bus should not be driven. during write leveling mode, only the nop or des commands are allowed. the memory controller should attempt to level only one rank at a time; thus, the outputs of other ranks should be disabled by setting mr1[12] to a ?1? in the other ranks. the memory controller may assert odt after a t mod delay as the dram will be ready to process the odt transition. odt should be turned on prior to dqs being driven low by at least odtl on delay (wl - 2 t ck), provided it does not violate the aforementioned t mod delay requirement. the memory controller may drive dqs low and dqs# high after t wldqsen has been satisfied. the controller may begin to toggle dqs after t wlmrd (one dqs toggle is dqs transitioning from a low state to a high st ate with dqs# transitioning from a high state to a low state, then both transition back to their original states). at a minimum, odtl on and t aon must be satisfied at least one clock prior to dqs toggling. after t wlmrd and a dqs low preamble ( t wpre) have been satisfied, the memory controller may provide either a single dqs toggle or multiple dqs toggles to sample ck for a given dqs-to-ck skew. each dqs toggle must not violate t dqsl (min) and t dqsh (min) specifications. t dqsl (max) and t dqsh (max) specifications are not applicable during write leveling mode. the dqs must be able to distinguish the ck?s rising edge within t wls and t wlh. the prime dq will output the ck?s status asynchronously from the associated dqs rising edge ck capture within t wlo. the remaining dq that always drive low when dqs is toggling must be low within t wloe after the first t wlo is satisfied (the prime dq going low). as previously noted, dqs is an input and not an output during this pr ocess. figure 49 on page 104 depicts the basic timing parameters for the overall write leveling procedure. the memory controller will likely sample ea ch applicable prime dq state and determine whether to increment or decrement its dqs delay setting. after the memory controller performs enough dqs toggles to detect th e ck?s ?0-to-1? transition, the memory controller should lock the dqs delay setting for that dram. after locking the dqs setting, leveling for the rank will have been achieved, and the write leveling mode for the rank should be disabled or reprogrammed (i f write leveling of another rank follows).
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 104 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram commands figure 49: write leveling sequence notes: 1. mrs: load mr1 to enter write leveling mode. 2. nop: nop or des. 3. dqs, dqs# needs to fulf ill minimum pulse width re q uirements t dqsh (min) and t dqsl (min) as defined for regular writes. th e maximum pulse width is system-dependent. 4. differential dqs is th e differential data strobe (dqs, dqs# ). timing reference points are the zero crossings. the solid line represents dqs; the dotted line represents dqs#. 5. dram drives leveling feedback on a prime dq (dq0 for x4 and x8). the remaining dq are driven low and remain in this stat e throughout the leveling procedure. write leveling mode exit procedure after the dram are leveled, they must exit from write leveling mode before the normal mode can be used. figure 50 on page 105 depicts a general procedure in exiting write leveling mode. after the last rising dqs (capturing a ?1? at t0), the memory controller should stop driving the dqs signals after t wlo (max) delay plus enough delay to enable the memory controller to capture the applic able prime dq state (at ~tb0). the dq balls become undefined when dqs no longer remains low, and they remain undefined until t mod after the mrs command (at te1). the odt input should be deasserted low su ch that odtl off (min) expires after the dqs is no longer driving low. when odt low satisfies t is, odt must be kept low (at ~tb0) until the dram is ready for either anot her rank to be leveled or until the normal mode can be used. after dqs termination is switched off, write level mode should be disabled via the mrs command (at tc2). after t mod is satisfied (at te1), any valid command may be registered by the dram. some mrs commands may be issued after t mrd (at td1). c k c k# c omman d t1 t2 early remainin g dq late remainin g dq t wloe nop 2 nop mr s 1 nop nop nop nop nop nop nop nop nop t wl s t wl s t wlh t wlh don ? t c are un d efine d drivin g mo d e in d i c ates a break in time sc ale prime dq 5 differential dq s 4 odt t mod t dq s l 3 t dq s l 3 t dq s h 3 t dq s h 3 t wlo t wlmrd t wldq s en t wlo t wlo t wlo
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 105 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram commands figure 50: exit write leveling notes: 1. the dq result, ?= 1,? between ta0 and tc0, is a result of the dqs, dq s# signals capturing ck high just after the t0 state. nop c k t0 t1 t2 ta0 t b 0t c 0t c 1t c 2t d 0t d 1 te0 te1 c k# c omman d odt r tt _dq nop nop nop nop nop nop mr s nop nop a dd ress mr1 vali d vali d vali d vali d don ? t c are transitionin g r tt dq s , r tt dq s #r tt _ nom un d efine d drivin g mo d e t aof (max) t mrd in d i c ates a break in time sc ale dq s , dq s # c k = 1 dq t i s t aof (min) t mod t wlo + t wloe odtl off
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 106 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations operations initialization the following sequence is required for power up and initialization, as shown in figure 51 on page 107: 1. apply power. reset# is recommended to be below 0.2 v dd q during power ramp to ensure the outputs remain disabled (high-z) and odt off (r tt is also high-z). all other inputs, including odt, may be undefined. during power up, either of the following conditions may exist and must be met: ? condition a: ?v dd and v dd q are driven from a single-power converter output and are ramped with a maximum delta voltage between them of v 300mv. slope reversal of any power supply signal is allowed. the voltage levels on all balls other than v dd , v dd q, v ss , v ss q must be less than or equal to v dd q and v dd on one side, and must be greater than or equal to v ss q and v ss on the other side. ?both v dd and v dd q power supplies ramp to v dd (min) and v dd q (min) within t v ddpr = 200ms. ?v ref dq tracks v dd 0.5, v ref ca tracks v dd 0.5. ?v tt is limited to 0.95v when the power ramp is complete and is not applied directly to the device; however, t vtd should be greater than or equal to zero to avoid device latchup. ? condition b: ?v dd may be applied before or at the same time as v dd q. ?v dd q may be applied before or at the same time as v tt , v ref dq, and v ref ca. ? no slope reversals are allowed in the power supply ramp for this condition. 2. until stable power, maintain reset# low to ensure the outputs remain disabled (high-z). after the power is stable, reset# must be low for at least 200s to begin the initialization process. odt will remain in the high-z state while reset# is low and until cke is registered high. 3. cke must be low 10ns prior to reset# transitioning high. 4. after reset# transitions high, wait 500s (minus one clock) with cke low. 5. after this cke low time, cke may be br ought high (synchronously) and only nop or des commands may be issued. the clock must be present and valid for at least 10ns (and a minimum of five clocks) and odt must be driven low at least t is prior to cke being registered high. when cke is re gistered high, it must be continuously registered high until the full initialization process is complete. 6. after cke is registered high and after t xpr has been satisfied, mrs commands may be issued. issue an mrs (load mode) comman d to mr2 with the applicable settings (provide low to ba2 and ba0 and high to ba1). 7. issue an mrs command to mr3 with the applicable settings. 8. issue an mrs command to mr1 with the applicable settings, including enabling the dll and configuring odt. 9. issue an mrs command to mr0 with the a pplicable settings, including a dll reset command. t dllk (512) cycles of clock inpu t are required to lock the dll. 10. issue a zqcl command to calibrate r tt and r on values for the process voltage tem- perature (pvt). prior to normal operation, t zq init must be satisfied. 11. when t dllk and t zq init have been satisfied, the ddr3 sdram will be ready for nor- mal operation.
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 107 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations figure 51: initialization sequence c ke r tt ba[2:0] all volta g e supplies vali d an d sta b le t = 200s (min) dm dq s a dd ress a10 c k c k# t c l c omman d nop t0 ta0 don ? t c are t c l t i s t c k odt dq t b 0 t dllk mr1 with dll ena b le mr0 with dll reset t mrd t mod mr s mr s ba0 = h ba1 = l ba2 = l ba0 = l ba1 = l ba2 = l c o d e c o d e c o d e c o d e vali d vali d vali d vali d normal operation mr2 mr3 t mrd t mrd mr s mr s ba0 = l ba1 = h ba2 = l ba0 = h ba1 = h ba2 = l c o d e c o d e c o d e c o d e t c 0t d 0 v tt v ref v dd q v dd re s et# t = 500s (min) t c k s rx s ta b le an d vali d c lo c k vali d power-up ramp t (max) = 200ms dram rea d y for external c omman d s t1 t zq init zq c ali b ration a10 = h zq c l t i s s ee power-up c on d itions in the initialization sequen c e text, set up 1 t xpr vali d = 20ns t io z in d i c ates a break in time sc ale t (min) = 10ns t vtd
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 108 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations mode registers mode registers (mr0?mr3) are used to define various modes of programmable opera- tions of the ddr3 sdram. a mode register is programmed via the mode register set (mrs) command during initialization, and it retains the stored information (except for mr0[8] which is self-clearing) until it is either reprogrammed, reset# goes low, or until the device loses power. contents of a mode register can be altered by reexecuting the mrs command. if the user chooses to modify only a subset of the mode register?s variables, all variables must be programmed when the mrs command is issued. reprogramming the mode register will not alter the contents of the memory array, provided it is performed correctly. the mrs command can only be issued (or reissued) when all banks are idle and in the precharged state ( t rp is satisfied and no data bursts are in progress). after an mrs command has been issued, two parameters must be satisfied: t mrd and t mod. the controller must wait t mrd before initiating any subsequent mrs commands (see figure 52). figure 52: mrs-to-mrs command timing ( t mrd) notes: 1. prior to issuing th e mrs command, all banks must be idle and precharged, t rp (min) must be satisfied, and no data bursts can be in progress. 2. t mrd specifies the mrs-to-mrs command minimum cycle time. 3. cke must be registered hi gh from the mrs command until t mrspden (min) (see "power- down mode" on page 151). 4. for a cas la tency change, t xpdll timing must be met be fore any nonmrs command. the controller must also wait t mod before initiating any nonmrs commands (excluding nop and des), as shown in figure 53 on page 109. the dram requires t mod in order to update the requested features, with the exception of dll reset, which requires additional time. until t mod has been satisfied, the updated features are to be assumed unavailable. vali d vali d mr s 1 mr s 2 nop nop nop nop t0 t1 t2 ta0 ta1 ta2 c k# c k c omman d a dd ress c ke 3 don ? t c are in d i c ates a break in time sc ale t mrd
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 109 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations figure 53: mrs-to-nonmrs command timing ( t mod) notes: 1. prior to issuin g the mrs command, all banks must be idle (they must be precharged, t rp must be satisfied, an d no data bursts can be in progress). 2. prior to ta2 when t mod (min) is being satisfied, no commands (except nop/des) may be issued. 3. if r tt was previously enabled, odt must be registered low at t0 so that odtl is satisfied prior to ta1. odt must also be registered lo w at each rising ck edge from t0 until t mod (min) is satisfied at ta2. 4. cke must be registered high from the mrs command until t mrspden (min), at which time power-down may occur (see "power-down mode" on page 151). mode register 0 (mr0) the base register, mr0, is used to define various ddr3 sdram modes of operation. these definitions include the selection of a burst length, burst type, cas latency, oper- ating mode, dll reset, write recovery, and precharge power-down mode, as shown in figure 54 on page 110. burst length burst length is defined by mr0[ 1: 0] (see figure 54 on page 110). read and write accesses to the ddr3 sdram are burst-oriented, with the burst length being programmable to ?4? (chop mode), ?8? (fixed), or selectab le using a12 during a read/write command (on-the-fly). the burst length determines the maximum number of column locations that can be accessed for a given read or write command. when mr0[1:0] is set to ?01? during a read/write command, if a12 = 0, then bc4 (chop) mode is selected. if a12 = 1, then bl8 mode is selected. specific timing diagrams, and turnaround between read/write, are shown in the read/w rite sections of this document. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses fo r that burst take place within this block, meaning that the burst will wrap within the bl ock if a boundary is reached. the block is uniquely selected by a[ i :2] when the burst length is set to ?4? and by a[ i :3] when the burst length is set to ?8? (where a i is the most significant column address bit for a given configuration). the remaining (least significan t) address bit(s) is (are) used to select the starting location within the block. the prog rammed burst length a pplies to both read and write bursts. vali d vali d mr s non mr s nop nop nop nop t0 t1 t2 ta0 ta1 ta2 c k# c k c omman d a dd ress c ke vali d up d atin g settin g ol d settin g new settin g don ? t c are in d i c ates a break in time sc ale t mod
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 110 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations figure 54: mode register 0 (mr0) definitions notes: 1. mr0[16, 13, 7, 2] are reserved for future use and must be programmed to ?0.? burst type accesses within a given burst may be programmed to either a sequential or an inter- leaved order. the burst type is selected via mr0[3], as shown in figure 54. the ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address, as shown in ta ble 68 on page 111. ddr3 only supports 4-bit burst chop and 8-bit burst access modes. full interleave address ordering is supported for reads, while writes are restricted to nibble (bc4) or word (bl8) boundaries. 0 1 bl cas# latency bt pd a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register 0 (mr0) address bus 976543 8210 a10 a12 a11 ba0 ba1 10 11 12 13 m3 0 1 read burst type se q uential (nibble) interleaved cas latency reserved 5 6 7 8 9 10 11 (ddr3-1600) m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 m6 0 0 0 0 1 1 1 1 15 dll write recovery reserved 5 6 7 8 10 12 reserved wr 0 0 m12 0 1 precharge pd dll off (slow exit) dll on (fast exit) ba2 16 0 1 burst length fixed bl8 4 or 8 (on-the-fly via a12) fixed bc4 (chop) reserved m0 0 1 0 1 m1 0 0 1 1 m9 0 1 0 1 0 1 0 1 m10 0 0 1 1 0 0 1 1 m11 0 0 0 0 1 1 1 1 m14 0 1 0 1 m15 0 0 1 1 mode register mode register 0 (mr0) mode register 1 (mr1) mode register 2 (mr2) mode register 3 (mr3) a13 14 0 1 0 1 m8 0 1 dll reset no yes
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 111 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations notes: 1. internal read and write operations start at the same point in time for bc4 as they do for bl8. 2. z = data and strobe output drivers are in tri-state. 3. v = a valid logic level (0 or 1), but the respec tive input buffer ignore s level-on input pins. 4. x = ?don?t care.? dll reset dll reset is defined by mr0[8] (see figure 54 on page 110). programming mr0[8] to ?1? activates the dll reset function. mr0[8] is self-clearing, meaning it returns to a value of ?0? after the dll reset function has been initiated. anytime the dll reset function is initiated, cke must be high and the clock held stable for 512 ( t dllk) clock cycles before a read command can be issued. this is to allow time for the internal clock to be sync hronized with the external clock. failing to wait for synchronization to occur may result in invalid output timing specifications, such as t dqsck timings. write recovery write recovery time is defined by mr0[11:9] (see figure 54 on page 110). write recovery values of 5, 6, 7, 8, 10, or 12 may be used by programming mr0[11:9]. the user is required to program the correct value of write recovery and is calculated by dividing t wr (ns) by t ck (ns) and rounding up a noninteger value to the next integer: wr (cycles) = roundup ( t wr [ns]/ t ck [ns]). table 68: burst order burst length read/ write starting column address (a[2, 1, 0]) burst type = sequential (decimal) burst type = interleaved (decimal) notes 4 chop read 0 0 0 0, 1, 2, 3, z, z, z, z 0, 1, 2, 3, z, z, z, z 1, 2 0 0 1 1, 2, 3, 0, z, z, z, z 1, 0, 3, 2, z, z, z, z 1, 2 0 1 0 2, 3, 0, 1, z, z, z, z 2, 3, 0, 1, z, z, z, z 1, 2 0 1 1 3, 0, 1, 2, z, z, z, z 3, 2, 1, 0, z, z, z, z 1, 2 1 0 0 4, 5, 6, 7, z, z, z, z 4, 5, 6, 7, z, z, z, z 1, 2 1 0 1 5, 6, 7, 4, z, z, z, z 5, 4, 7, 6, z, z, z, z 1, 2 1 1 0 6, 7, 4, 5, z, z, z, z 6, 7, 4, 5, z, z, z, z 1, 2 1 1 1 7, 4, 5, 6, z, z, z, z 7, 6, 5, 4, z, z, z, z 1, 2 write 0 v v 0, 1, 2, 3, x, x, x, x 0, 1, 2, 3, x, x, x, x 1, 3, 4 1 v v 4, 5, 6, 7, x, x, x, x 4, 5, 6, 7, x, x, x, x 1, 3, 4 8 read 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 1 0 0 1 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 1 0 1 0 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 1 0 1 1 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 1 1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 1 1 0 1 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 1 1 1 0 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 1 1 1 1 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0 1 write v v v 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 1, 3
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 112 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations precharge power-down (precharge pd) the precharge pd bit applies only when precharge power-down mode is being used. when mr0[12] is set to ?0,? the dll is off during precharge power-down providing a lower standby current mode; however, t xpdll must be satisfied when exiting. when mr0[12] is set to ?1,? the dll continues to run during precharge power-down mode to enable a faster exit of precharge power-down mode; however, t xp must be satisfied when exiting (see "power-down mode" on page 151). cas latency (cl) the cl is defined by mr0[6:4], as shown in figure 54 on page 110. cas latency is the delay, in clock cycles, between the internal read command and the availability of the first bit of output data. the cl can be se t to 5, 6, 7, 8, 9, or 10. ddr3 sdram do not support half-clock latencies. examples of cl = 6 and cl = 8 are shown in figure 55. if an internal read command is registered at clock edge n , and the cas latency is m clocks, the data will be available nominally coincident with clock edge n + m. table 49 on page 63 through table 51 on page 65 indicate the cls supported at various operating frequencies. figure 55: read latency notes: 1. for illustration purposes, on ly cl = 6 and cl = 8 are shown. other cl values are possible. 2. shown with nominal t dqsck and nominal t dsdq. read nop nop nop nop nop nop nop ck ck# command dq dqs, dqs# dqs, dqs# t0 t1 t2 t3 t4 t5 t6 t7 t8 don?t care ck ck# command dq read nop nop nop nop nop nop nop t0 t1 t2 t3 t4 t5 t6 t7 t8 di n + 3 di n + 1 di n + 2 di n + 4 di n di n nop nop al = 0, cl = 8 al = 0, cl = 6 transitioning data
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 113 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations mode register 1 (mr1) the mode register 1 (mr1) controls addition al functions and features not available in the other mode registers: q off (output disable), tdqs (for the x8 configuration only), dll enable/dll disable, r tt _ nom value (odt), write leveling, posted cas additive latency, and output drive strength. these functions are controlled via the bits shown in figure 56. the mr1 register is programmed via the mrs command and retains the stored information until it is reprogrammed, until reset# goes low, or until the device loses power. reprogramming the mr1 register will not alter the contents of the memory array, provided it is performed correctly. the mr1 register must be loaded when all banks are idle and no bursts are in progress. the controller must satisfy the specified timing parameters t mrd and t mod before initiating a subsequent operation. figure 56: mode register 1 (mr1) definition notes: 1. mr1[16, 13, 10, 8] ar e reserved for future use an d must be programmed to ?0.? 2. during write leveling, if mr1[7] and mr1[12] are ?1? then all r tt _ nom values are available for use. 3. during write leveling, if mr1[7] is a ?1,? but mr1[12] is a ?0,? then only r tt _ nom write val- ues are available for use. dll enable/dll disable the dll may be enabled or disabled by pr ogramming mr1[0] during the load mode command, as shown in figure 56. the dll mu st be enabled for normal operation. dll enable is required during power-up initiali zation and upon returning to normal opera- tion after having disabled the dll for the purpose of debugging or evaluation. enabling the dll should always be followed by re setting the dll using the appropriate load mode command. if the dll is enabled prior to entering self refresh mode, the dll is automatically disabled when entering self refresh oper ation and is automatically reenabled and reset upon exit of self refresh operation. if the dll is disabled prior to entering self refresh mode, the dll remains disabled even upon exit of self refresh operation until it is reenabled and reset. al r tt q off a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register 1 (mr1) address bus 9 7 6 5 4 3 8 2 1 0 a10 a12 a11 ba0 ba1 10 11 12 13 m0 0 1 dll enable enable (normal) disable m5 0 0 1 1 output drive strength rzq/6 (40 [nom]) rzq/7 (34 [nom]) reserved reserved 14 wl 1 0 ods dll r tt tdqs m12 0 1 q off enabled disabled ba2 15 0 1 m7 0 1 write levelization disable (normal) enable additive latency (al) disabled (al = 0) al = cl - 1 al = cl - 2 reserved m3 0 1 0 1 m4 0 0 1 1 r tt ods m1 0 1 0 1 a13 16 0 1 m11 0 1 tdqs disabled enabled 0 1 0 1 r tt _ nom (odt) 2 non-writes r tt _ nom disabled rzq/4 (60 [nom]) rzq/2 (120 [nom]) rzq/6 (40 [nom]) rzq/12 (20 [nom]) rzq/8 (30 [nom]) reserved reserved r tt _ nom (odt) 3 writes r tt _ nom disabled rzq/4 (60 [nom]) rzq/2 (120 [nom]) rzq/6 (40 [nom]) n/a n/a reserved reserved m2 0 1 0 1 0 1 0 1 m6 0 0 1 1 0 0 1 1 m9 0 0 0 0 1 1 1 1 mode register mode register set 0 (mr0) mode register set 1 (mr1) mode register set 2 (mr2) mode register set 3 (mr3) m14 0 1 0 1 m15 0 0 1 1
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 114 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations the dram is not tested to check?nor does micron warrant compliance with?normal mode timings or functionality when the dll is disabled. an attempt has been made to have the dram operate in the normal mode where reasonably possible when the dll has been disabled; however, by industry standard, a few known exceptions are defined: 1. odt is not allowed to be used. 2. the output data is no longer edge-aligned to the clock. 3. cl and cwl can only be six clocks. when the dll is disabled, timing and functi onality can vary from the normal operation specifications when the dll is enabled (see ?dll disable mode? on page 96). disabling the dll also implies the need to change the clock frequency (see ?input clock frequency change? on page 99). output drive strength the ddr3 sdram uses a programmable impedance output buffer. the drive strength mode register setting is defined by mr1[5, 1]. rzq/7 (34 [nom]) is the primary output driver impedance setting for ddr3 sdram de vices. to calibrate the output driver impedance, an external precision resistor (rzq) is connected between the zq ball and v ss q. the value of the resistor must be 240 1 percent. the output impedance is set during initialization. additional impedance calibration updates do not affect device operation, and all data sheet timings and current specifica- tions are met during an update. to m e et the 34 specification, the output drive strength must be set to 34 during initialization. to obtain a calibrated output driver impedance after power-up, the ddr3 sdram needs a calibration command that is pa rt of the initialization and reset proce- dure. output enable/disable the output enable function is defined by mr1[12], as shown in figure 56 on page 113. when enabled (mr1[12] = 0), all outp uts (dq, dqs, dqs#) function when in the normal mode of operation. when disa bled (mr1[12] = 1), all ddr3 sdram outputs (dq and dqs, dqs#) are tri-stated. the output disable feature is intended to be used during i dd characterization of the read current and during t dqss margining (write leveling) only. tdqs enable termination data strobe (tdqs) is a feature of the x8 ddr3 sdram configuration, which provides termination resistance (r tt ), that may be useful in some system config- urations. tdqs is not supported in x4 or x 16 configurations. when enabled via the mode register (mr1[11]), the r tt that is applied to dqs and dqs# is also applied to tdqs and tdqs#. in contrast to the rdqs function of ddr2 sdram, tdqs provides the termina- tion resistance r tt only. the output data strobe fu nction of rdqs is not provided by tdqs; thus, r on does not apply to tdqs and tdqs#. the tdqs and dm functions share the same ball. when the tdqs function is enabled via the mode register, the dm function is not supported. when the tdqs function is disabled, the dm function is provided, and the tdqs# ball is not used. the tdqs function is available in the x8 ddr3 sdram configuration only and must be disabled via the mode register for the x4 and x16 configurations.
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 115 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations on-die termination odt resistance r tt _ nom is defined by mr1[9, 6, 2] (see figure 56 on page 113). the r tt termination value applies to the dq, dm, dqs, dqs#, and tdqs, tdqs# balls. ddr3 supports multiple r tt termination values based on rzq/ n where n can be 2, 4, 6, 8, or 12 and rzq is 240 . unlike ddr2, ddr3 odt must be turned off pr ior to reading data out and must remain off during a read burst. r tt _ nom termination is allowed an y time after the dram is initialized, calibrated, and not performing read access, or when it is not in self refresh mode. additionally, write accesses with dynamic odt enabled (r tt _ wr ) temporarily replaces r tt _ nom with r tt _ wr . the actual effective termination, r tt _ eff , may be different from the r tt targeted due to nonlinearity of the termination. for r tt _ eff values and calculations (see "on-die termination (odt)" on page 160). the odt feature is designed to improve signal integrity of the memory channel by enabling the ddr3 sdram controller to independently turn on/off odt for any or all devices. the odt input control pi n is used to determine when r tt is turned on (odtl on) and off (odtl off ), assuming odt has been enabled via mr1[9, 6, 2]. timings for odt are detailed in "on-die termination (odt)" on page 160. write leveling the write leveling function is enabled by mr1[7], as shown in figure 56 on page 113. write leveling is used (during initialization) to deskew the dqs strobe to clock offset as a result of fly-by topology designs. for better signal integrity, ddr3 sdram memory modules adopted fly-by topology for the commands, addresses, control signals, and clocks. the fly-by topology benefits from a reduced number of stubs and their lengths. however, fly-by topology induces flight time skews between the clock and dqs strobe (and dq) at each dram on the dimm. controllers will have a difficult time maintaining t dqss, t dss, and t dsh specifications without supporting write leveling in systems which use fly-by topology-based modules. write leveling timing and detailed operation informa- tion is provided in ?write leveling? on page 101. posted cas additive latency (al) al is supported to make the command and data bus efficient for sustainable band- widths in ddr3 sdram. mr1[4, 3] define the value of al as shown in figure 57 on page 116. mr1[4, 3] enable the user to prog ram the ddr3 sdram with an al = 0, cl - 1, or cl - 2. with this feature, the ddr3 sdram enables a read or write command to be issued after the activate command for that bank prior to t rcd (min). the only restriction is activate to read or write + al t rcd (min) must be satisfied. assuming t rcd (min) = cl, a typical application using this feature sets al = cl - 1 t ck = t rcd (min) - 1 t ck. the read or write command is held for the time of the al before it is released internally to the ddr3 sdram device. read latency (rl) is controlled by the sum of the al and cas latency (cl), rl = al + cl. write latency (wl) is the sum of cas write latency and al, wl = al + cwl (see "mode register 2 (mr2)" on page 116). examples of read and write latencies are shown in figure 57 on page 116 and figure 59 on page 117.
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 116 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations figure 57: read latency (al = 5, cl = 6) mode register 2 (mr2) the mode register 2 (mr2) controls addition al functions and features not available in the other mode registers. these additional functions are cas write latency (cwl), auto self refresh (asr), self refresh temperature (srt), and dynamic odt (r tt _ wr ). these functions are controlled via the bits shown in figure 58. the mr2 is programmed via the mrs command and will retain the stored information until it is programmed again or until the device loses power. reprogramming the mr2 register will not alter the contents of the memory array, provided it is performed correctly. the mr2 register must be loaded when all banks are id le and no data bursts are in progress, and the controller must wa it the specified time t mrd and t mod before initiating a subse- quent operation. figure 58: mode register 2 (mr2) definition notes: 1. mr2[16, 13:11, 8, and 2:0] are reserved for future use and must all be programmed to ?0.? ck ck# command dq dqs, dqs# active n t0 t1 don?t care nop nop t6 t12 nop read n t13 nop do n + 3 do n + 2 do n + 1 rl = al + cl = 11 t14 nop do n t rcd (min) al = 5 cl = 6 t11 bc4 indicates a break in time scale transitioning data t2 nop m 1 4 0 1 0 1 m 1 5 0 0 1 1 mo d e regi s ter mo d e re g ister set 0 (mr0) mo d e re g ister set 1 (mr1) mo d e re g ister set 2 (mr2) mo d e re g ister set 3 (mr3) a9 a7 a 6 a5 a4 a3 a8 a2 a1 a0 mo d e re g ister 2 (mr2) a dd ress b us 97 6 543 8 2 1 0 a10 a12 a11 ba0 ba1 1 0 11 1 2 1 3 1 4 1 5 1 c wl 0 1 0 ba2 a s r 16 0 1 a13 0 1 0 1 0 1 0 1 0 1 0 1 s rt r tt _ wr m 6 0 1 auto s elf refre s h (optional) disa b le d : manual ena b le d : automati c m7 0 1 s elf refre s h temperature normal (0 c to 85 c ) exten d e d (0 c to 95 c ) ca s write laten c y (cwl) 5 c k ( t c k 2.5ns) 6 c k (2.5ns > t c k 1.875ns) 7 c k (1.875ns > t c k 1.5ns) 8 c k (1.5ns > t c k 1.25ns) reserve d reserve d reserve d reserve d m3 0 1 0 1 0 1 0 1 m4 0 0 1 1 0 0 1 1 m5 0 0 0 0 1 1 1 1 m9 0 1 0 1 m 1 0 0 0 1 1 dynami c odt ( r tt _ wr ) r tt _ wr d isa b le d rzq/4 rzq/2 reserve d
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 117 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations cas write latency (cwl) cwl is defined by mr2[5:3] and is the delay, in clock cycles, from the releasing of the internal write to the latching of the first da ta in. cwl must be correctly set to the corre- sponding operating clock frequency (see figure 58 on page 116). the overall write latency (wl) is equal to cwl + al (figure 56 on page 113), as shown in figure 59. figure 59: cas write latency auto self refresh (asr) mode register mr2[6] is used to disable/enable the asr function. when asr is disabled, the self refresh mode?s refresh rate is assumed to be at the normal 85c limit (sometimes referred to as 1x refres h rate). in the disabled mode, asr requires the user to ensure the dram never exceeds a t c of 85c while in self refresh unless the user enables the srt feature listed below when the t c is between 85c and 95c. enabling asr assumes the dram self refresh rate is changed automatically from 1x to 2x when the case temperature exceeds 85c. this enables the user to operate the dram beyond the standard 85c limit up to the optional extended temperature range of 95c while in self refresh mode. the standard self refresh current test specifies test conditions to normal case tempera- ture (85c) only, meaning if asr is enabled, the standard self refresh current specifica- tions do not apply (see ?extended temperature usage? on page 150). self refresh temperature (srt) mode register mr2[7] is used to disable/enable the srt function. when srt is disabled, the self refresh mode?s refresh rate is assumed to be at the normal 85c limit (sometimes referred to as 1x refresh rate). in the disabled mode, srt requires the user to ensure the dram never exceeds a t c of 85c while in self refresh mode unless the user enables asr. when srt is enabled, the dram self refresh is changed internally from 1x to 2x, regard- less of the case temperature. this enable s the user to operate the dram beyond the standard 85c limit up to the optional exte nded temperature range of 95c while in self refresh mode. the standard self refresh curren t test specifies test conditions to normal case temperature (85c) only, meaning if sr t is enabled, the standard self refresh current specifications do not apply (see ?e xtended temperature usage? on page 150). ck ck# command dq dqs, dqs# active n bc4 t0 t1 don?t care nop nop t6 t12 nop write n t13 nop di n + 3 di n + 2 di n + 1 t14 nop di n t rcd (min) nop al = 5 t11 indicates a break in time scale wl = al + cwl = 11 transitioning data t2 cwl = 6
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 118 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations srt vs. asr if the normal case temperature limit of 85c is not exceeded, then neither srt nor asr is required, and both can be disabled througho ut operation. however, if the extended temperature option of 95c is needed, the user is required to provide a 2x refresh rate during (manual) refresh and to enable either the srt or the asr to ensure self refresh is performed at the 2x rate. srt forces the dram to switch the internal self refresh rate from 1x to 2x. self refresh is performed at the 2x refresh rate regardless of the case temperature. asr automatically switches the dram?s internal self refresh rate from 1x to 2x. however, while in self refresh mode, asr enables the refresh rate to automatically adjust between 1x to 2x over the supported temperature range. one other disadvantage with asr is the dram cannot always switch from a 1x to a 2x refresh rate at an exact case temperature of 85c. although the dram will support data integrity when it switches from a 1x to a 2x refresh rate, it may switch at a lower temperature than 85c. since only one mode is neccesary, srt and asr cannot be enabled at the same time. dynamic odt the dynamic odt (r tt _ wr ) feature is defined by mr2[10, 9]. dynamic odt is enabled when a value is selected. this new ddr3 sdram feature enables the odt termination value to change without issuing an mrs co mmand, essentially changing the odt termi- nation ?on-the-fly.? with dynamic odt (r tt _ wr ) enabled, the dram switches from normal odt (r tt _ nom ) to dynamic odt (r tt _ wr ) when beginning a write burs t and subsequently switches back to odt (r tt _ nom ) at the completion of the write burst. if r tt _ nom is disabled, the r tt _ nom value will be high-z. special timing parameters must be adhered to when dynamic odt (r tt _ wr ) is enabled: odtl cnw , odtl cnw 4, odtl cnw 8, odth4, odth8, and t adc. dynamic odt is only applicable during write cycles. if odt (r tt _ nom ) is disabled, dynamic odt (r tt _ wr ) is still permitted. r tt _ nom and r tt _ wr can be used indepen- dent of one other. dynamic odt is not available during write leveling mode, regardless of the state of odt (r tt _ nom ). for details on dynamic odt operation, refer to ?on-die termination (odt)? on page 160.
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 119 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations mode register 3 (mr3) the mode register 3 (mr3) controls addition al functions and features not available in the other mode registers. currently define d is the multipurpose register (mpr). this function is controlled via the bits shown in figure 60. the mr3 is programmed via the load mode command and retains the stor ed information until it is programmed again or until the device loses power. reprogramming the mr3 register will not alter the contents of the memory array, provided it is performed correctly. the mr3 register must be loaded when all banks are idle and no data bursts are in progress, and the controller must wait the specified time t mrd and t mod before initiating a subsequent operation. figure 60: mode register 3 (mr3) definition notes: 1. mr3[16 and 13:4] are reserved for fu ture use and must all be programmed to ?0.? 2. when mpr control is set for normal dram operation, mr3[1, 0] will be ignored. 3. intended to be used for read synchronization. multipurpose register (mpr) the multipurpose register function is used to output a predefined system timing calibration bit sequence. bit 2 is the master bit that enables or disables access to the mpr register, and bits 1 and 0 determine which mode the mpr is placed in. the basic concept of the multipurpose register is shown in figure 61 on page 120. if mr3[2] is a ?0,? then the mpr access is disabled, and the dram operates in normal mode. however, if mr3[2] is a ?1,? then the dram no longer outputs normal read data but outputs mpr data as defined by mr3[0, 1] . if mr3[0, 1] is equal to ?00,? then a predefined read pattern for system calibration is selected. to enable the mpr, the mrs command is i ssued to mr3, and mr3[2] = 1 (see table 69 on page 120). prior to issuing the mrs command , all banks must be in the idle state (all banks are precharged, and t rp is met). when the mpr is enabled, any subsequent read or rdap commands are redirected to the multipurpose register. the resulting operation when either a read or a rdap command is issued, is defined by mr3[1:0] when the mpr is enabled (see table 70 on page 121). when the mpr is enabled, only read or rdap commands are allowed until a subseque nt mrs command is issued with the mpr disabled (mr3[2] = 0). power-down mode, self refresh, and any other nonread/rdap command is not allowed during mpr enable mode. the reset function is supported during mpr enable mode. a9 a7 a 6 a5 a4 a3 a8 a2 a1 a0 mo d e re g ister 3 (mr3) a dd ress b us 97 6 543 8 2 1 0 a10 a12 a11 ba0 ba1 1 0 11 1 2 1 3 1 4 1 5 a13 10 1 0 1 0 1 0 1 0 1 0 1 0 1 mpr 1 ba2 16 0 1 0 1 0 1 0 1 0 1 m2 0 1 mpr ena b le normal dram operations 2 dataflow from mpr mpr_rf m 1 4 0 1 0 1 m 1 5 0 0 1 1 mo d e regi s ter mo d e re g ister set (mr0) mo d e re g ister set 1 (mr1) mo d e re g ister set 2 (mr2) mo d e re g ister set 3 (mr3) mpr read fun c tion pre d efine d pattern 3 reserve d reserve d reserve d m0 0 1 0 1 m 1 0 0 1 1
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 120 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations figure 61: multipurpose register (mpr) block diagram notes: 1. a predefined data pattern can be read out of the mpr with an external read command. 2. mr3[2] defines whether the da ta flow comes from the memory core or the mpr. when the data flow is defined, the mpr contents can be read out continuously with a regular read or rdap command. mpr functional description the mpr is a 1-bit-wide logical interface via all dq balls during a read command. dq0 on a x4 and a x8 is the prime dq and outp uts the mpr data while the remaining dq are driven low. similarly, for the x16, dq0 (lower byte) and dq8 (upper byte) are the prime dq and output the mpr data while the re maining dq drive low. the mpr readout supports fixed read burst and read burst chop (mrs and otf via a12/bc#) with regular read latencies and ac timings applicable, provided the dll is locked as required. mpr addressing for a valid mpr read is as follows: ? a[1:0] must be set to ?00? as the burst order is fixed per nibble ?a2 selects the burst order: ? bl8, a2 is set to ?0,? and the burst order is fixed to 0, 1, 2, 3, 4, 5, 6, 7 ? for burst chop 4 cases, the burst order is switched on the nibble base and: ? a2 = 0; burst order = 0, 1, 2, 3 ? a2 = 1; burst order = 4, 5, 6, 7 ? burst order bit 0 (the first bit) is assigned to lsb, and burst order bit 7 (the last bit) is assigned to msb table 69: mpr functional description of mr3 bits mr3[2] mr3[1:0] function mpr mpr read function 0 ?don?t care? normal operat ion, no mpr transaction all subse q uent reads come from the dram memory array all subse q uent writes go to the dram memory array 1 a[1:0] (see table 70 on page 121) enable mpr mode, subse q uent read/rdap commands defined by bits 1 and 2 memory c ore mr3[2] = 0 (mpr off) dq, dm, dq s , dq s # multipurpose re g ister pre d efine d d ata for reads mr3[2] = 1 (mpr on)
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 121 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations ? a[9:3] are a ?don?t care? ? a10 is a ?don?t care? ? a11 is a ?don?t care? ? a12: selects burst chop mode on-t he-fly, if enabled within mr0 ? a13 is a ?don?t care? ? ba[2:0] are a ?don?t care? mpr register address definitions and bursting order the mpr currently supports a single data form at. this data format is a predefined read pattern for system calibration. the predefin ed pattern is always a repeating 0?1 bit pattern. examples of the different types of predefined read pattern bursts are shown in figure 62 on page 122, figure 63 on page 123, figure 64 on page 124, and figure 65 on page 125. notes: 1. burst order bit 0 is assigned to lsb, and bu rst order bit 7 is assigned to msb of the selected mpr agent. table 70: mpr readouts and burst order bit mapping mr3[2] mr3[1:0] function burst length read a[2:0] burst order and data pattern 1 00 read predefined pattern for system calibration bl8 000 burst order: 0, 1, 2, 3, 4, 5, 6, 7 predefined pattern: 0, 1, 0, 1, 0, 1, 0, 1 bc4 000 burst order: 0, 1, 2, 3 predefined pattern: 0, 1, 0, 1 bc4 100 burst order: 4, 5, 6, 7 predefined pattern: 0, 1, 0, 1 1 01 rfu n/a n/a n/a n/a n/a n/a n/a n/a n/a 1 10 rfu n/a n/a n/a n/a n/a n/a n/a n/a n/a 1 11 rfu n/a n/a n/a n/a n/a n/a n/a n/a n/a
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 122 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations figure 62: mpr system read calibration wi th bl8: fixed burst order single readout notes: 1. read with bl8 ei ther by mrs or otf. 2. memory controller mu st drive 0 on a[2:0]. t0 ta0 t b 0t b 1t c 0t c 1t c 2t c 3t c 4t c 5 t c6 t c 7t c 8t c 9t c 10 c k c k# mr s prea read 1 nop nop nop nop nop nop nop nop mr s nop nop vali d c omman d t mprr don ? t c are in d i c ates a break in time sc ale dq s , dq s # bank a dd ress 3 vali d 3 0 a[1:0] vali d 0 2 1 a2 0 2 0 00 a[9:3] vali d 00 0 1 a10/ap vali d 0 0 a11 vali d 0 0 a12/b c # vali d 1 0 0 a[15:13] vali d 0 dq t mod t rp t mod rl
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 123 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations figure 63: mpr system read calibration with bl8: fixed burst order, back-to-back readout notes: 1. read with bl8 ei ther by mrs or otf. 2. memory controller mu st drive 0 on a[2:0]. t0 ta t b t c 0t c 1t c 2t c 3 t c 4t c 5t c6 t c 7t c 8t c 9t c 10 t d c k c k# t mprr don ? t c are in d i c ates a break in time sc ale rl 3 vali d 3 bank a dd ress vali d a[1:0] vali d 0 2 0 2 0 a2 1 2 0 2 1 0 0 a[15:13] vali d vali d 0 a[9:3] vali d vali d 00 00 a11 vali d vali d 0 0 a12/b c # vali d 1 0 0 a10/ap vali d vali d 0 0 1 rl prea read 1 nop nop nop nop nop nop nop nop nop mr s vali d c omman d read 1 mr s dq vali d dq s , dq s # t rp t mod t cc d t mod
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 124 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations figure 64: mpr system read calibration with bc4: lowe r nibble, then upper nibble notes: 1. read with bc4 either by mrs or otf. 2. memory controller mu st drive 0 on a[1:0]. 3. a2 = 0 selects lower 4 nibble bits 0 . . . 3. 4. a2 = 1 selects upper 4 nibble bits 4 . . . 7. t0 ta t b c k c k# dq dq s , dq s # t mod t mprr don ? t c are t c 0t c 1t c 2t c 3t c 4t c 5t c6 t c 7t c 8t c 9t c 10 t d nop nop nop nop nop mr s nop nop vali d c omman d mr s prea read 1 read 1 nop nop in d i c ates a break in time sc ale bank a dd ress 3 vali d 3 vali d 0 a[1:0] vali d 0 2 0 2 1 a2 1 4 0 3 0 00 a[9:3] vali d vali d 00 0 1 a10/ap vali d vali d 0 0 a11 vali d vali d 0 0 a12/b c # vali d 1 vali d 1 0 0 a[15:13] vali d vali d 0 rl rl t rf t mod t cc d
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 125 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations figure 65: mpr system read calibration with bc4: uppe r nibble, then lower nibble notes: 1. read with bc4 either by mrs or otf. 2. memory controller mu st drive 0 on a[1:0]. 3. a2 = 1 selects upper 4 nibble bits 4 . . . 7. 4. a2 = 0 selects lower 4 nibble bits 0 . . . 3. t0 ta t b 0 1 a10/ap vali d vali d 0 c k c k# mr s prea read 1 read 1 nop nop nop nop nop nop nop mr s nop nop vali d c omman d 0 0 4 1 3 1 a2 t mod t mprr 3 vali d 3 bank a dd ress vali d 0 2 0 2 0 a[1:0] vali d 0 0 a[15:13] vali d vali d 0 0 a11 vali d vali d 00 00 a[9:3] vali d vali d don ? t c are t c 0t c 1t c 2t c 3t c 4t c 5t c6 t c 7t c 8t c 9t c 10 t d in d i c ates a break in time sc ale rl dq dq s , dq s # 0 a12/b c # vali d 1 vali d 1 0 rl t rf t mod t cc d
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 126 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations mpr read predefined pattern the predetermined read calibration pattern is a fixed pattern of 0, 1, 0, 1, 0, 1, 0, 1. the following is an example of using the read out predetermined read calibration pattern. the example is to perform multiple reads from the multipurpose register in order to do system level read timing calibration based on the predetermined and standardized pattern. the following protocol outlines the step s used to perform the read calibration: ? precharge all banks ?after t rp is satisfied, set mrs, mr3[2] = 1 and mr3[1:0] = 00. this redirects all subse- quent reads and loads the predefined pattern into the mpr. as soon as t mrd and t mod are satisfied, the mpr is available ? data write operations are not allowed until the mpr returns to the normal dram state ? issue a read with burst order information (all other address pins are ?don?t care?): ? a[1:0] = 00 (data burst order is fixed starting at nibble) ? a2 = 0 (for bl8, burst order is fixed as 0, 1, 2, 3, 4, 5, 6, 7) ? a12 = 1 (use bl8) ? after rl = al + cl, the dram bursts out the predefined read calibration pattern (0,1,0,1,0,1,0,1) ? the memory controller repeats the calibr ation reads until read data capture at memory controller is optimized ? after the last mpr read burst and after t mprr has been satisfied, issue mrs, mr3[2] = 0, and mr3[1:0] = ?don?t care? to the normal dram state. all subsequent read and write accesses will be regular reads and writes from/to the dram array ?when t mrd and t mod are satisfied from the last mrs, the regular dram commands (such as activate a memory bank for regu lar read or write access) are permitted mode register set (mrs) the mode registers are loaded via inputs ba[2:0], a[13:0]. ba[2:0] determine which mode register is programmed: ? ba2 = 0, ba1 = 0, ba0 = 0 for mr0 ? ba2 = 0, ba1 = 0, ba0 = 1 for mr1 ? ba2 = 0, ba1 = 1, ba0 = 0 for mr2 ? ba2 = 0, ba1 = 1, ba0 = 1 for mr3 the mrs command can only be issued (or reissued) when all banks are idle and in the precharged state ( t rp is satisfied and no data bursts are in progress). the controller must wait the specified time t mrd before initiating a subseque nt operation such as an acti- vate command (see figure 52 on page 108). th ere is also a restriction after issuing an mrs command with regard to when the up dated functions become available. this parameter is specified by t mod. both t mrd and t mod parameters are shown in figure 52 on page 108 and figure 53 on page 1 09. violating either of these requirements will result in unspecified operation. zq calibration the zq calibration command is used to calibrate the dram output drivers (r on ) and odt values (r tt ) over process, voltage, and te mperature, provided a dedicated 240 (1 percent) external resistor is connected from the dram?s zq ball to v ss q.
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 127 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations ddr3 sdram need a longer time to calibrate r on and odt at power-up initialization and self refresh exit and a relatively shorter time to perform periodic calibrations. ddr3 sdram defines two zq calibration comm ands: zq calibration long (zqcl) and zq calibration short (zqcs). an exampl e of zq calibration timing is shown in figure 66. all banks must be precharged and t rp must be met before zqcl or zqcs commands can be issued to the dram. no other activities (other than another zqcl or zqcs command may be issued to another dram) ca n be performed on the dram channel by the controller for the duration of t zq init or t zq oper . the quiet time on the dram channel helps accurately calibrate r on and odt. after dram ca libration is achieved, the dram should disable the zq ball?s cu rrent consumption path to reduce power. zq calibration commands can be issued in parallel to dll reset and locking time. upon self refresh exit, an explicit zqcl is required if zq calibration is desired. in dual-rank systems that share the zq resist or between devices, the controller must not allow overlap of t zq init , t zq oper , or t zq cs between ranks. figure 66: zq calibration timing (zqcl and zqcs) notes: 1. cke must be continuously registered high during the calibration procedure. 2. odt must be disabled via th e odt signal or the mrs during the calibration procedure. 3. all devices connected to the dq bus should be high-z during calibration. activate before any read or write commands can be issued to a bank within the dram, a row in that bank must be opened (activated). this is accomplished via the activate command, which selects both the ba nk and the row to be activated. after a row is opened with an activate command, a read or write command may be issued to that row, subject to the t rcd specification. however, if the additive latency is programmed correctly, a read or write command may be issued prior to t rcd (min). in this operation, the dram enables a read or write command to be issued after the activate command for that bank, but prior to t rcd (min) with the requirement that (activate-to-read/write) + al t rcd (min) (see "posted cas additive latency (al)" on page 115). t rcd (min) should be divided by the clock period and rounded up nop zq c l nop nop vali d vali d zq cs nop nop nop vali d c omman d in d i c ates a break in time sc ale t0 t1 ta0 ta1 ta2 ta3 t b 0t b 1t c 0t c 1t c 2 a dd ress vali d vali d vali d a10 vali d vali d vali d c k c k# don ? t c are dq hi g h-z hi g h-z 3 3a c tivities a c tiv- ities vali d vali d odt 2 2 vali d 1 c ke 1 vali d vali d vali d t zq cs t zq init or t zq oper
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 128 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations to the next whole number to determine th e earliest clock edge after the activate command on which a read or write command can be entered. the same procedure is used to convert other specification limi ts from time units to clock cycles. when at least one bank is open, any re ad-to-read command delay or write-to- write command delay is restricted to t ccd (min). a subsequent activate command to a different row in the same bank can only be issued after the previous active row has been closed (precharged). the minimum time interval between successive activate commands to the same bank is defined by t rc. a subsequent activate command to another ba nk can be issued whil e the first bank is being accessed, which results in a reduction of total row-access overhead. the minimum time interval between successive activate commands to different banks is defined by t rrd. no more than four bank activate commands may be issued in a given t faw (min) period, and the t rrd (min) restriction still applies. the t faw (min) param- eter applies, regardless of the number of banks already opened or closed. figure 67: example: meeting t rrd (min) and t rcd (min) figure 68: example: t faw c omman d don ? t c are t1 t0 t2 t3 t4 t5 t8 t9 t rrd row row c ol bank x bank y bank y nop a c t nop nop a c t nop nop rd/wr t r c d ba[2:0] c k# a dd ress c k t10 t11 nop nop in d i c ates a break in time sc ale c omman d don ? t c are t1 t0 t4 t5 t8 t9 t10 t11 t rrd row row bank a bank b row bank c row bank d bank y row bank y nop a c t nop a c ta c t nop nop t faw ba[2:0] c k# a dd ress c k t19 t20 nop a c ta c t bank e in d i c ates a break in time sc ale
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 129 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations read read bursts are initiated with a read command. the starting column and bank addresses are provided with the read comm and and auto precharge is either enabled or disabled for that burst access. if auto pr echarge is enabled, the row being accessed is automatically precharged at the completion of the burst. if auto precharge is disabled, the row will be left open after the completion of the burst. during read bursts, the valid data-out elem ent from the starting column address is available read latency (rl) clocks later. rl is defined as the sum of posted cas addi- tive latency (al) and cas latency (cl) (rl = al + cl). the value of al and cl is programmable in the mode register via th e mrs command. each subsequent data-out element will be valid nominally at the next positive or negative clock edge (that is, at the next crossing of ck and ck#). figure 69 shows an example of rl based on a cl setting of 8 and an al setting of 0. figure 69: read latency notes: 1. do n = data-out from column n . 2. subse q uent elements of data-out appear in the programmed order following do n . dqs, dqs# is driven by the dram along with the output data. the initial low state on dqs and high state on dqs# is known as the read preamble ( t rpre). the low state on dqs and the high state on dqs#, coincident with the last data-out element, is known as the read postamble ( t rpst). upon completion of a burst, assuming no other commands have been initiated, the dq will go high-z. a detailed explanation of t dqsq (valid data-out skew), t qh (data-out window hold), an d the valid data window are depicted in figure 80 on page 137. a detailed explanation of t dqsck (dqs transition skew to ck) is also depicted in figure 80 on page 137. data from any read burst may be concatenated with data from a subsequent read command to provide a continuous flow of data. the first data element from the new burst follows the last element of a complete d burst. the new read command should be issued t ccd cycles after the first read command. this is shown for bl8 in figure 70 on page 131. if bc4 is enabled, t ccd must still be met which will cause a gap in the data output, as shown in figure 71 on page 131. no nconsecutive read data is reflected in figure 72 on page 132. ddr3 sdram do not allow interrupting or truncating any read burst. c k c k# c omman d read nop nop nop nop nop nop nop a dd ress bank a , c ol n c l = 8, al = 0 dq dq s , dq s # do n t0 t7 t8 t9 t10 t11 don ? t c are transitionin g data t12 t12 in d i c ates a break in time sc ale
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 130 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations data from any read burst must be completed before a subsequent write burst is allowed. an example of a read burst followed by a write burst for bl8 is shown in figure 73 on page 132 (bc4 is shown in figure 74 on page 133). to ensure the read data is completed before the write data is on the bus, the minimum read-to-write timing is rl + t ccd - wl + 2 t ck. a read burst may be followed by a precha rge command to the same bank provided auto precharge is not activated. th e minimum read-to-precharge command spacing to the same bank is four clocks an d must also satisfy a minimum analog time from the read command. this time is called t rtp (read-to-precharge). t rtp starts al cycles later than the read command. examples for bl8 are shown in figure 75 on page 133 and bc4 in figure 76 on page 134. following the precharge command, a subsequent command to the same bank cannot be issued until t rp is met. the precharge command followed by another precharge command to the same bank is allowed. however, the precharge period will be determined by the last precharge command issued to the bank. if a10 is high when a read command is issued, the read with auto precharge function is engaged. the dram starts an auto precha rge operation on the rising edge which is al + t rtp cycles after the read command. dram support a t ras lockout feature (see figure 78 on page 134). if t ras (min) is not satisfied at the edge, the starting point of the auto precharge operation will be delayed until t ras (min) is satisfied. if t rtp (min) is not satisfied at the edge, the starting poin t of the auto precharge operation will be delayed until t rtp (min) is satisfied. in case the internal precharge is pushed out by t rtp, t rp starts at the point at which the inte rnal precharge happens (not at the next rising clock edge after this event). the time from read with auto precharge to the next activate command to the same bank is al + ( t rtp + t rp)*, where ?*? means rounded up to the next integer. in an y event, internal precharge does not start earlier than four clocks after the last 8 n -bit prefetch.
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 131 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations figure 70: consecutive read bursts (bl8) notes: 1. nop commands are shown for ease of illustrati on; other commands may be valid at these times. 2. the bl8 setting is activated by either mr0[1:0] = 00 or mr0[1:0] = 01 and a12 = 1 during read command at t0 and t4. 3. do n (or b ) = data-out from column n (or column b ). 4. bl8, rl = 5 (cl = 5, al = 0). figure 71: consecutive read bursts (bc4) notes: 1. nop commands are shown for ease of illustrati on; other commands may be valid at these times. 2. the bc4 setting is activated by either mr0[1:0] = 10 or mr0[1:0] = 01 and a12 = 0 du ring read command at t0 and t4. 3. do n (or b ) = data-out from column n (or column b ). 4. bc4, rl = 5 (cl = 5, al = 0). t0 t1 t2 t3 t4 t5 t 6 t7 t8 t9 t10 t11 don ? t c are transitionin g data t12 t13 t14 t rp s t nop read read nop nop nop nop nop nop nop nop nop nop nop nop c k c k# c omman d 1 dq 3 dq s , dq s # bank, c ol n bank, c ol b a dd ress 2 rl = 5 t rpre t cc d rl = 5 do n + 3 do n + 2 do n + 1 do n do n + 7 do n + 6 do n + 5 do n + 4 do b + 3 do b + 2 do b + 1 do b do b + 7 do b + 6 do b + 5 do b + 4 nop c k c k# c omman d 1 dq 3 dq s , dq s # t0 t1 t2 t3 t4 t5 t 6 t7 t8 t9 a dd ress 2 t10 t11 don ? t c are transitionin g data t12 t13 t14 read read nop nop nop nop nop nop nop nop nop nop nop nop bank, c ol n bank, c ol b t rp s t t rpre t rp s t t rpre rl = 5 do n + 3 do n + 2 do n + 1 do n do b + 3 do b + 2 do b + 1 do b rl = 5 t cc d
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 132 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations figure 72: nonconsecutive read bursts notes: 1. al = 0, rl = 8. 2. do n (or b ) = data-out from column n (or column b ). 3. seven subse q uent elements of data-out appear in the programmed order following do n . 4. seven subse q uent elements of data-out appear in the programmed order following do b . figure 73: read (bl8) to write (bl8) notes: 1. nop commands are shown for ease of illustrati on; other commands may be valid at these times. 2. the bl8 setting is activated by either mr0[1:0] = 00 or mr0[1:0] = 01 and a12 = 1 during the read command at t0, and the write command at t6. 3. do n = data-out from column, di b = data-in for column b . 4. bl8, rl = 5 (al = 0, cl = 5), wl = 5 (al = 0, cwl = 5). don ? t c are transitionin g data t0 t1 t2 t3 t4 t5 t 6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t1 6 t17 dq s , dq s # c omman d nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop read nop read a dd ress bank a, c ol n bank a, c ol b c k c k# dq do n do b c l = 8 c l = 8 don ? t c are transitionin g data t0 t1 t2 t3 t4 t5 t 6 t7 t8 t9 t10 t11 t12 t13 t14 t15 c k c k# c omman d 1 nop nop nop nop nop write nop nop nop nop nop nop nop nop nop t wp s t t rpre t wpre t rp s t dq s , dq s # dq 3 wl = 5 t wr t wtr read do n do n + 1 do n + 2 do n + 3 do n + 4 do n + 5 do n + 6 do n + 7 di n di n + 1 di n + 2 di n + 3 di n + 4 di n + 5 di n + 6 di n + 7 read-to-write c omman d d elay = rl + t cc d + 2 t c k - wl t bl = 4 c lo c ks a dd ress 2 bank, c ol b bank, c ol n rl = 5
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 133 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations figure 74: read (bc4) to write (bc4) otf notes: 1. nop commands are shown for ease of illustrati on; other commands may be valid at these times. 2. the bc4 otf setting is activated by mr0[1:0] and a12 = 0 during read comma nd at t0 and write command at t4. 3. do n = data-out from column n ; di n = data-in from column b . 4. bc4, rl = 5 (al - 0, cl = 5), wl = 5 (al = 0, cwl = 5). figure 75: read to precharge (bl8) don ? t c are transitionin g data t0 t1 t2 t3 t4 t5 t 6 t7 t8 t9 t10 t11 t12 t13 t14 t15 c k c k# a dd ress 2 bank, c ol n bank, c ol b c omman d 1 read nop nop nop write nop nop nop nop nop nop nop nop nop nop nop t wp s t t wpre t rp s t dq s , dq s # dq 3 wl = 5 read-to-write c omman d d elay = rl + t cc d/2 + 2 t c k - wl t wr t wtr t bl = 4 c lo c ks t rpre rl = 5 do n do n + 1 do n + 2 do n + 3 di n di n + 1 di n + 2 di n + 3 t ra s t rtp c k c k# c omman d nop nop nop nop a dd ress dq dq s , dq s # don ? t c are transitionin g data nop nop nop nop nop a c t nop nop nop nop t0 t1 t2 t3 t4 t5 t 6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t1 6 t17 nop read bank a , c ol n nop pre bank a , (or all) bank a , row b t rp do n do n + 1 do n + 2 do n + 3 do n + 4 do n + 5 do n + 6 do n + 7
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 134 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations figure 76: read to precharge (bc4) figure 77: read to precharge (al = 5, cl = 6) figure 78: read with auto precharge (al = 4, cl = 6) c k c k# don ? t c are transitionin g data t0 t1 t2 t3 t4 t5 t 6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t1 6 t17 c omman d nop nop nop nop nop nop nop nop nop a c t nop nop nop nop nop read nop pre a dd ress bank a, c ol n bank a, (or all) bank a, row b t rp t rtp dq s , dq s # dq do n do n + 1 do n + 2 do n + 3 t ra s c k c k# c omman d nop nop nop nop a dd ress dq dq s , dq s # don ? t c are transitionin g data nop nop nop nop nop t0 t1 t2 t3 t4 t5 t 6 t7 t8 t9 t10 t11 t12 t13 t14 t15 nop read bank a , c ol n nop pre bank a, (or all) a c t bank a , row b nop nop t ra s c l = 6 al = 5 t rtp t rp do n + 3 do n + 2 do n do n + 1 c k c k# c omman d nop nop nop nop a dd ress dq dq s , dq s # don ? t c are transitionin g data nop nop nop nop nop t0 t1 t2 t3 t4 t5 t 6 t7 t8 t9 t10 t11 t12 t13 ta0 t rtp (min) nop read nop al = 4 nop nop c l = 6 nop t ra s (min) a c t in d i c ates a break in time sc ale t rp bank a , c ol n bank a , row b do n do n + 1 do n + 2 do n + 3
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 135 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations a dqs to dq output timing is shown in figure 79 on page 136. the dq transitions between valid data outputs must be within t dqsq of the crossing point of dqs, dqs#. dqs must also maintain a minimum high and low time of t qsh and t qsl. prior to the read preamble, the dq balls will either be floating or terminated depending on the status of the odt signal. figure 80 on page 137 shows the strobe-to-cl ock timing during a read. the crossing point dqs, dqs# must transition within t dqsck of the clock crossing point. the data out has no timing relationship to clock, only to dqs, as shown in figure 80 on page 137. figure 80 on page 137 also shows the read preamble and postamble. normally, both dqs and dqs# are high-z to save power (v dd q). prior to data output from the dram, dqs is driven low and dqs# is high for t rpre. this is known as the read preamble. the read postamble, t rpst, is one half clock from the last dqs, dqs# transition. during the read postamble, dqs is driven low and dqs# is high. when complete, the dq will either be disabled or will cont inue terminating depending on the state of the odt signal. figure 85 on page 140 demonstrates how to measure t rpst.
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 136 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations figure 79: data output timing ? t dqsq and data valid window notes: 1. nop commands are shown for ease of illustrati on; other commands may be valid at these times. 2. the bl8 setting is activated by either mr0[1, 0] = 0, 0 or mr0[0, 1] = 0, 1 and a12 = 1 during read command at t0. 3. do n = data-out from column n . 4. bl8, rl = 5 (al = 0, cl = 5). 5. output timings ar e referenced to v dd q/2 and dll on and locked. 6. t dqsq defines the skew between dq s, dqs# to data and does no t define dqs, dqs# to clock. 7. early data transitions may not always happen at the same dq . data transitions of a dq can vary (either early or late) within a burst. t0 t1 t2 t3 t4 t5 t 6 t7 t8 t9 t10 bank, c ol n t rp s t nop read nop nop nop nop nop nop nop nop nop c k c k# c omman d 1 a dd ress 2 t dq s q (max) dq s , dq s # dq 3 (last d ata vali d ) dq 3 (first d ata no lon g er vali d ) all dq c olle c tively do n do n + 3 do n + 2 do n + 1 do n + 7 do n + 6 do n + 5 do n + 4 do n + 2 do n + 1 do n + 7 do n + 6 do n + 5 do n + 4 do n + 3 do n + 2 do n + 1 do n do n + 7 do n + 6 do n + 5 do n do n + 3 t rpre don ? t c are transitionin g data data vali d data vali d t qh t qh t hz (dq) max do n + 4 rl = al + c l t dq s q (max) t lz (dq) min
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 137 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations t hz and t lz transitions occur in the same access time as valid data transitions. these parameters are referenced to a specific voltage level which specifies when the device output is no longer driving t hz (dqs) and t hz (dq) or begins driving t lz (dqs), t lz (dq). figure 81 shows a method to calculate the point when the device is no longer driving t hz (dqs) and t hz (dq) or begins driving t lz (dqs), t lz (dq) by measuring the signal at two different voltages. the actual voltage measurement points are not critical as long as the calculation is consistent. the parameters t lz (dqs), t lz (dq), t hz (dqs), and t hz (dq) are defined as single-ended. figure 80: data strobe timing ? reads figure 81: method for calculating t lz and t hz notes: 1. within a burst, the rising strobe edge is not necessarily fixed at t dqsck (min) or t dqsck (max). instead, the rising str obe edge can vary between t dqsck (min) and t dqsck (max). 2. the dqs high pulse width is defined by t qsh, and the dqs low pulse width is defined by t qsl. likewise, t lz (dqs) min and t hz (dqs) min are not tied to t dqsck (min) (early strobe case) and t lz (dqs) max and t hz (dqs) max are not tied to t dqsck (max) (late strobe case); however, they tend to track one another. 3. the minimum pulse width of the read preamble is defined by t rpre (min). the minimum pulse width of the read postamble is defined by t rpst (min). rl measured to this point dqs, dqs# early strobe ck t dqsck (min) t lz (dqs) min t hz (dqs) min dqs, dqs# late strobe t dqsck (max) t lz (dqs) max t hz (dqs) max t dqsck (min) t dqsck (min) t dqsck (max) t dqsck (max) t dqsck (max) t dqsck (min) ck# t rpre t qsh t qsl t qsl t qsl t qsl t qsh t qsh t qsh bit 0 bit 1 bit 2 bit 7 t rpre bit 0 bit 1 bit 2 bit 7 bit 6 bit 3 bit 4 bit 5 bit 6 bit 4 bit 3 bit 5 t rpst t rpst t0 t1 t2 t3 t4 t5 t6 t hz (dq s ), t hz (dq) t hz (dq s ), t hz (dq) en d point = 2 t1 - t2 v oh - x mv v tt - x mv v ol + x mv v tt + x mv v oh - 2 x mv v tt - 2 x mv v ol + 2 x mv v tt + 2 x mv t lz (dq s ), t lz (dq) t lz (dq s ), t lz (dq) b e g in point = 2 t1 - t2 t1 t1 t2 t2
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 138 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations figure 82: t rpre timing figure 83: t rpst timing t rpre dq s - dq s # dq s dq s # t1 t rpre b e g ins t2 t rpre en d s c k c k# v tt resultin g d ifferential si g nal relevant for t rpre spe c ifi c ation t c t a t b t d s in g le-en d e d si g nal provi d e d as b a c k g roun d information 0v s in g le-en d e d si g nal provi d e d as b a c k g roun d information v tt v tt t rp s t dq s - dq s # dq s dq s # t1 t rp s t b e g ins t2 t rp s t en d s resultin g d ifferential si g nal relevant for t rp s t spe c ifi c ation c k c k# v tt t c t a t b t d s in g le-en d e d si g nal, provi d e d as b a c k g roun d information s in g le-en d e d si g nal, provi d e d as b a c k g roun d information 0v v tt v tt
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 139 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations write write bursts are initiated with a write command. the starting column and bank addresses are provided with the write command, and auto precharge is either enabled or disabled for that access. if auto precharge is selected, the row being accessed will be precharged at the end of the write burst. if auto precharge is not selected, the row will remain open for subsequent accesses. af ter a write command has been issued, the write burst may not be interrupted. fo r the generic write commands used in figure 86 on page 141 through figure 94 on page 146, auto precharge is disabled. during write bursts, the first valid data-in elem ent is registered on a rising edge of dqs following the write latency (wl) clocks late r and subsequent data elements will be registered on successive edges of dqs. wr ite latency (wl) is defined as the sum of posted cas additive latency (al) and ca s write latency (cwl): wl = al + cwl. the values of al and cwl are programmed in the mr0 and mr2 registers, respectively. prior to the first valid dqs edge, a full cycle is needed (including a dummy crossover of dqs, dqs#) and specified as the write preamble shown in figure 86 on page 141. the half cycle on dqs following the last data-in element is known as the write postamble. the time between the write command and the first valid edge of dqs is wl clocks t dqss. figure 87 on page 142 through figure 94 on page 146 show the nominal case where t dqss = 0ns; however, figure 86 on page 141 includes t dqss (min) and t dqss (max) cases. data may be masked from completing a wr ite using data mask. the mask occurs on the dm ball aligned to the write data. if dm is low, the write completes normally. if dm is high, that bit of data is masked. upon completion of a burst, assuming no ot her commands have been initiated, the dq will remain high-z, and any additional input data will be ignored. data for any write burst may be concatenat ed with a subsequent write command to provide a continuous flow of input data. the new write command can be t ccd clocks following the previous write command. the first data element from the new burst is applied after the last element of a complete d burst. figures 87 and 88 on page 142 show concatenated bursts. an example of nonconse cutive writes is shown in figure 89 on page 143. data for any write burst may be followed by a subsequent read command after t wtr has been met (see figures 90 and 91 on page 144 and figure 92 on page 145). data for any write burst may be follow ed by a subsequent precharge command providing t wr has been met, as shown in figure 93 on page 146 and figure 94 on page 146. both t wtr and t wr starting time may vary depending on the mode register settings (fixed bc4, bl8 vs. otf).
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 140 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations figure 84: t wpre timing figure 85: t wpst timing dq s - dq s # t1 t wpre b e g ins t2 t wpre en d s t wpre resultin g d ifferential si g nal relevant for t wpre spe c ifi c ation 0v c k c k# v tt t wp s t dq s - dq s # t1 t wp s t b e g ins t2 t wp s t en d s resultin g d ifferential si g nal relevant for t wp s t spe c ifi c ation 0v c k c k# v tt
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 141 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations figure 86: write burst notes: 1. nop commands are shown for ease of illus tration; other commands may be valid at these times. 2. the bl8 setting is activated by either mr0[1: 0] = 00 or mr0[1:0] = 01 and a12 = 1 during the write command at t0. 3. di n = data-in for column n . 4. bl8, wl = 5 (al = 0, cwl = 5). 5. t dqss must be met at each rising clock edge. 6. t wpst is usually depicted as ending at the crossing of dqs, dqs#; however, t wpst actually ends when dqs no longer drives low and dqs# no longer drives high. di n + 3 di n + 2 di n + 1 di n t0 t1 t2 t3 t4 t5 t 6 t7 t8 t9 t10 don ? t c are transitionin g data di n + 7 di n + 6 di n + 5 di n + 4 bank, c ol n nop write nop nop nop nop nop nop nop nop nop c k c k# c omman d 1 dq 3 dq s , dq s # a dd ress 2 t wp s t t wpre t wp s t t dq s l dq 3 dq 3 t wp s t dq s , dq s # dq s , dq s # t dq s l t wpre t dq ss t dq ss t d s h t d s h t d s h t d s h t d ss t d ss t d ss t d ss t d ss t d ss t d ss t d ss t d ss t d ss t d s h t d s h t d s h t d s h t dq s l t dq s h t dq s l t dq s h t dq s l t dq s h t dq s h t dq s l t dq s l t dq s l t dq s l t dq s h t dq s h t dq s h t dq s h t dq s l t dq s h t dq s l t dq s h t dq s h t dq s l t dq s h t dq s l t dq s h t dq s l t dq s h t dq s h wl = al + c wl t dq ss (min) t dq ss (nom) t dq ss (max) t dq s l t wpre di n + 3 di n + 2 di n + 1 di n di n + 7 di n + 6 di n + 5 di n + 4 di n + 3 di n + 2 di n + 1 di n di n + 7 di n + 6 di n + 5 di n + 4
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 142 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations figure 87: consecutive write (bl8) to write (bl8) notes: 1. nop commands are shown for ease of illustrati on; other commands may be valid at these times. 2. the bl8 setting is activated by either mr0[1:0] = 00 or mr0[1:0] = 01 and a12 = 1 during the write commands at t0 and t4. 3. di n (or b ) = data-in for column n (or column b ). 4. bl8, wl = 5 (al = 0, cwl = 5). figure 88: consecutive write (bc4) to write (bc4) via mrs or otf notes: 1. nop commands are shown for ease of illustrati on; other commands may be valid at these times. 2. bc4, wl = 5 (al = 0, cwl = 5). 3. di n (or b ) = data-in for column n (or column b ). 4. the bc4 setting is activated by mr0[1:0] = 01 an d a12 = 0 during the write command at t0 and t4. wl = 5 wl = 5 t0 t1 t2 t3 t4 t5 t 6 t7 t8 t9 t cc d t wpre t10 t11 don ? t c are transitionin g data t12 t13 t14 vali d vali d nop write write nop nop nop nop nop nop nop nop nop nop nop nop c k c k# c omman d 1 dq 3 dq s , dq s # a dd ress 2 t wp s t t wr t wtr t bl = 4 c lo c ks di n + 3 di n + 2 di n + 1 di n di n + 7 di n + 6 di n + 5 di n + 4 di b + 3 di b + 2 di b + 1 di b di b + 7 di b + 6 di b + 5 di b + 4 wl = 5 wl = 5 t0 t1 t2 t3 t4 t5 t 6 t7 t8 t9 t cc d t wpre t10 t11 don ? t c are transitionin g data t12 t13 t14 vali d vali d nop write write nop nop nop nop nop nop nop nop nop nop nop nop c k c k# c omman d 1 dq 3 dq s , dq s # a dd ress 2 t wp s t t wr t wtr t wp s t t wpre di n + 3 di n + 2 di n + 1 di n di b + 3 di b + 2 di b + 1 di b t bl = 4 c lo c ks
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 143 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations figure 89: nonconsecutive write to write notes: 1. di n (or b ) = data-in for column n (or column b ). 2. seven subse q uent elements of data-in are applied in the programmed order following do n . 3. each write command may be to any bank. 4. shown for wl = 7 (cwl = 7, al = 0). figure 90: write (bl8) to read (bl8) notes: 1. nop commands are shown for ease of illustrati on; other commands may be valid at these times. 2. t wtr controls the write-to-read delay to th e same device and starts with the first rising clock edge after the last write data shown at t9. 3. the bl8 setting is activated by either mr0[1:0] = 00 or mr0[1:0] = 01 and mr0[12] = 1 du ring the write command at t0. the read command at ta0 can be either bc4 or bl8, depending on mr0[1:0] and the a12 status at ta0. 4. di n = data-in for column n . 5. rl = 5 (al = 0, cl = 5), wl = 5 (al = 0, cwl = 5). c k c k# c omman d nop nop nop a dd ress dq dm dq s , dq s # transitionin g data nop nop nop nop nop nop nop nop nop nop t0 t1 t2 t3 t4 t5 t 6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t1 6 t17 nop write nop write vali d vali d nop di n di n + 1 di n + 2 di n + 3 di n + 4 di n + 5 di n + 6 don't c are di n + 7 di b di b + 1 di b + 2 di b + 3 di b + 4 di b + 5 di b + 6 di b + 7 wl = c wl + al = 7 wl = c wl + al = 7 wl = 5 t0 t1 t2 t3 t4 t5 t 6 t7 t8 t9 t wpre t10 t11 don ? t c are transitionin g data ta0 nop write read vali d vali d nop nop nop nop nop nop nop nop nop nop c k c k# c omman d 1 dq 4 dq s , dq s # a dd ress 3 t wp s t t wtr 2 in d i c ates a break in time sc ale di n + 3 di n + 2 di n + 1 di n di n + 7 di n + 6 di n + 5 di n + 4
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 144 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations figure 91: write to read (bc4 mode register setting) notes: 1. nop commands are shown for ease of illustrati on; other commands may be valid at these times. 2. t wtr controls the write-to-read delay to th e same device and starts with the first rising clock edge after the last write data shown at t7. 3. the fixed bc4 setting is activated by mr0[1:0] = 10 during th e write command at t0 and the read command at ta0. 4. di n = data-in for column n . 5. bc4 (fixed), wl = 5 (al = 0, cw l = 5), rl = 5 (al = 0, cl = 5). wl = 5 t0 t1 t2 t3 t4 t5 t 6 t7 t8 t9 ta0 don ? t c are transitionin g data nop write vali d read vali d nop nop nop nop nop nop nop nop c k c k# c omman d 1 dq 4 dq s , dq s # a dd ress 3 t wp s t t wtr 2 t wpre in d i c ates a break in time sc ale di n + 3 di n + 2 di n + 1 di n
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 145 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations figure 92: write (bc4 otf) to read (bc4 otf) notes: 1. nop commands are shown for ease of illustrati on; other commands may be valid at these times. 2. t wtr controls the write-to -read delay to the same device and starts after t bl. 3. the bc4 otf setting is activated by mr0[1:0] = 01 and a 12 = 0 during the write command at t0 and the read command at t n . 4. di n = data-in for column n . 5. bc4, rl = 5 (al = 0, cl = 5), wl = 5 (al = 0, cwl = 5). wl = 5 rl = 5 t0 t1 t2 t3 t4 t5 t 6 t7 t8 t9 t wpre t10 t11 don ? t c are transitionin g data tn nop write read vali d vali d nop nop nop nop nop nop nop nop nop c k c k# c omman d 1 dq 4 dq s , dq s # a dd ress 3 t wp s t t bl = 4 c lo c ks nop t wtr 2 in d i c ates a break in time sc ale di n + 3 di n + 2 di n + 1 di n
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 146 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations figure 93: write (bl8) to precharge notes: 1. di n = data-in from column n . 2. seven subse q uent elements of data-in are applie d in the programmed order following do n . 3. shown for wl = 7 (al = 0, cwl = 7). figure 94: write (bc4 mode register setting) to precharge notes: 1. nop commands are shown for ease of illus tration; other commands may be valid at these times. 2. the write recovery time ( t wr) is referenced from the first rising clock edge after the last write data is shown at t7. t wr specifies the last burst wr ite cycle until the precharge command can be issued to the same bank. 3. the fixed bc4 setting is activated by mr0[ 1:0] = 10 during the write command at t0. 4. di n = data-in for column n . 5. bc4 (fixed), wl = 5, rl = 5. t0 t1 t2 t3 t4 t5 t 6 t7 t8 t9 t10 t11 t12 ta0 ta1 di n + 3 di n + 2 di n + 1 di n di n + 6 di n + 7 di n + 5 di n + 4 nop write vali d nop nop nop nop nop nop nop nop nop nop nop nop pre c k c k# c omman d dq bl8 dq s , dq s # a dd ress don ? t c are transitionin g data in d i c ates a break in time sc ale t wr wl = al + c wl vali d t0 t1 t2 t3 t4 t5 t 6 t7 t8 t9 t10 t11 t12 ta0 ta1 di n + 3 di n + 2 di n + 1 di n nop write vali d nop nop nop nop nop nop nop nop nop nop nop nop pre c k c k# c omman d dq b c 4 dq s , dq s # a dd ress don ? t c are transitionin g data in d i c ates a break in time sc ale t wr wl = al + c wl vali d
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 147 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations figure 95: write (bc4 otf) to precharge notes: 1. nop commands are shown for ease of illus tration; other commands may be valid at these times. 2. the write recovery time ( t wr) is referenced from the rising clock edge at t9. t wr specifies the last burst write cycl e until the precharge command can be issued to the same bank. 3. the bc4 setting is activated by mr0[1:0] = 01 and a12 = 0 during the writ e command at t0. 4. di n = data-in for column n . 5. bc4 (otf), wl = 5, rl = 5. dq input timing figure 86 on page 141 shows the strobe to clock timing during a write. dqs, dqs# must transition within 0.25 t ck of the clock transitions as limited by t dqss. all data and data mask setup and hold timings are measured relative to the dqs, dqs# crossing, not the clock crossing. the write preamble and postamble are also show n. one clock prior to data input to the dram, dqs must be high and dqs# must be lo w. then for a half clock, dqs is driven low (dqs# is driven high) during the write preamble, t wpre. likewise, dqs must be kept low by the controller after the last data is written to the dram during the write postamble, t wpst. data setup and hold times are shown in figu re 96 on page 148. all setup and hold times are measured from the crossi ng points of dqs and dqs#. these setup and hold values pertain to data input and data mask input. additionally, the half period of the data input strobe is specified by t dqsh and t dqsl. wl = 5 t0 t1 t2 t3 t4 t5 t 6 t7 t8 t9 tn don ? t c are transitionin g data bank, c ol n nop write pre nop nop nop nop nop nop nop nop c k c k# c omman d 1 dq 4 dq s , dq s # a dd ress 3 t wp s t t wpre in d i c ates a break in time sc ale di n + 3 di n + 2 di n + 1 di n t wr 2 vali d
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 148 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations figure 96: data input timing precharge input a10 determines whether one bank or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba[2:0] select the bank. when all banks are to be precharged, inputs ba[2:0] are treated as ?don?t care.? after a bank is precharged, it is in the idle state and must be activated prior to any read or write commands being issued. self refresh the self refresh command is initiated like a refresh command except cke is low. the dll is automatically disabled upon entering self refresh and is automatically enabled and reset upon exiting self refresh. the dram must be idle with all banks in the precharge state ( t rp is satisfied and no bursts are in progress) before a self refresh entry command can be issued. odt must also be turned off before self refresh entry by registering the odt ball low prior to the self refresh entry command (see ?on-die termination (odt)? on page 160 for timing requirements). if r tt _ nom and r tt _ wr are disabled in the mode registers, odt can be a ?don?t care.? after the self refresh entry command is registered, cke must be held low to keep the dram in self refresh mode. after the dram has entered self refresh mode, all external control signals, except cke and reset#, become ?don?t care.? the dram initiates a minimum of one refresh command internally within the t cke period when it enters self refresh mode. the requirements for entering and exiting self refresh mode depend on the state of the clock during self refresh mode. first and fo remost, the clock must be stable (meeting t ck specifications) when self refresh mode is entered. if the clock remains stable and the frequency is not altered while in self refresh mode, then the dram is allowed to exit self refresh mode after t ckesr is satisfied (cke is allowed to transition high t ckesr later than when cke was registered low). since the clock remains stable in self refresh mode (no frequency change), t cksre and t cksrx are not required. however, if the clock is altered during self refresh mode (tur ned-off or frequency change), then t cksre and t cksrx must be satisfied. when entering self refresh mode, t cksre must be satisfied prior to altering the clock's frequency. prior to exiting self refresh mode, t cksrx must be satisfied prior to registering cke high. when cke is high during self refresh exit, nop or des must be issued for t xs time. t xs is required for the completion of any internal refresh that is already in progress and must be satisfied before a valid command not requiring a locked dll can be issued to the device. t xs is also the earliest time self refresh reentry may occur (see figure 97 on t dh t d s dm dq di b dq s , dq s # don ? t c are transitionin g data t dq s h t dq s l t wpre t wp s t
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 149 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations page 149). before a command requiring a lock ed dll can be applied, a zqcl command must be issued, t zq oper timing must be met, and t xsdll must be satisfied. odt must be off during t xsdll. figure 97: self refresh entry/exit timing notes: 1. the clock must be valid and stable meeting t ck specifications at least t cksre after entering self refresh mode, and at least t cksrx prior to exiting self refresh mode, if the clock is stopped or altered between states ta0 and tb0. if the clock remains valid and unchanged from entry and during se lf refresh mode, then t cksre and t cksrx do not apply; however, t ckesr must be satisfied prior to exiting at srx. 2. odt must be disabled and r tt off prior to entering self re fresh at state t1. if both r tt _ nom and r tt _ wr are disabled in the mode regist ers, odt can be a ?don?t care.? 3. self refresh entry (sre) is synchronous via a refresh command with cke low. 4. a nop or des command is re q uired at t2 after the sre comm and is issued prior to the inputs becoming ?don?t care.? 5. nop or des commands are re q uired prior to exiting self refresh mode until state te0. 6. t xs is re q uired before any commands not re q uiring a locked dll. 7. t xsdll is re q uired before any commands re q uiring a locked dll. 8. the device must be in the all banks idle state prior to entering self refresh mode. for exam- ple, all banks must be precharged, t rp must be met, and no data bursts can be in progress. 9. self refresh exit is asynchronous; however, t xs and t xsdll timings start at the first rising clock edge where cke high satisfies t isxr at tc1. t cksrx timing is also measured so that t isxr is satisfied at tc1. c k c k# c omman d nop nop 4 s re (ref) 3 a dd ress c ke odt 2 re s et# 2 vali d vali d 6 s rx (nop) nop 5 t rp 8 t x s 6 , 9 t x s dll 7, 9 odtl t i s t c pded t i s t i s enter self refresh mo d e (syn c hronous) exit self refresh mo d e (asyn c hronous) t0 t1 t2 t c 0t c 1t d 0 t b 0 don ? t c are te0 vali d vali d 7 vali d vali d vali d t ih ta0 tf0 in d i c ates a break in time sc ale t c k s rx 1 t c k s re 1 t c ke s r (min) 1
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 150 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations extended temperature usage micron?s ddr3 sdram support the optional ex tended temperature range of 0c to 95c, t c . thus, the srt and asr options must be used at a minimum. the extended temperature range dram must be refreshed externally at 2x (double refresh) anytime the case temperature is ab ove 85c (and does not exceed 95c). the external refreshing requirement is accomplished by reducing the refresh period from 64ms to 32ms. however, self refresh mode requires either asr or srt to support the extended temperature. thus either asr or srt must be enabled when t c is above 85c or self refresh cannot be used until the case temperature is at or below 85c. table 71 summarizes the two extended temperature options and table 72 summarizes how the two extended temperature options relate to one another. table 71: self refresh temperature and auto self refresh description field mr2 bits description self refresh temperature (srt) srt 7 if asr is disabled (mr2[6] = 0), srt must be programmed to indicate t oper during self refresh: *mr2[7] = 0: normal operating temperature range (0c to 85c) *mr2[7] = 1: extended operating temperature range (0c to 95c) if asr is enabled (mr2[7] = 1), srt must be set to 0, even if the extended temperature range is supported *mr2[7] = 0: srt is disabled auto self refresh (asr) asr 6 when asr is enabled, the dram automatically provides self refresh power management functions, (refresh rate for all supported operating temperature values) * mr2[6] = 1: asr is enabled (m7 must = 0) when asr is not enabled, the srt bit must be programmed to indicate t oper during self refresh operation * mr2[6] = 0: asr is disabled, must use manual self refresh temperature (srt) table 72: self refresh mode summary mr2[6] (asr) mr2[7] (srt) self refresh operation permitted operating temperature range for self refresh mode 0 0 self refresh mode is supp orted in the normal temperature range normal (0c to 85c) 0 1 self refresh mode is supported in normal and extended temperature ranges; when srt is enabled, it increases self refresh power consumption normal and extended (0c to 95c) 1 0 self refresh mode is supported in normal and extended temperature ranges; self refr esh power consumption may be temperature-dependent normal and extended (0c to 95c) 1 1 illegal
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 151 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations power-down mode power-down is synchronously entered when cke is registered low coincident with a nop or des command. cke is not allowed to go low while either an mrs, mpr, zqcal, read, or write operation is in progress. cke is allowed to go low while any of the other legal operations (such as row activation, precharge, auto precharge, or refresh) are in progress. however, the power-down i dd specifications are not appli- cable until such operations have been completed. depending on the previous dram state and the command issued prior to cke going low, certain timing constraints must be satisfied (as noted in table 73). timing diagrams detailing the different power-down mode entry and exits are shown in figure 98 on page 152 through figure 107 on page 157. notes: 1. if slow-exit mode precharge power-down is enabled and entered, odt becomes asynchro- nous t anpd prior to cke going low and remains asynchronous until t anpd + t xpdll after cke goes high. entering power-down disables the input and output buffers, excluding ck, ck#, odt, cke, and reset#. nop or des commands are required until t cpded has been satisfied, at which time all specified input/output buffers will be disabled. the dll should be in a locked state when power-down is entered for the fastest power-down exit timing. if the dll is not locked during power-down entry, the dll must be reset after exiting power- down mode for proper read operation as well as synchronous odt operation. during power-down entry, if any bank remains open after all in-progress commands are complete, the dram will be in active power-down mode. if all banks are closed after all in-progress commands are complete, the dram will be in precharge power-down mode. precharge power-down mode must be programmed to exit with either a slow exit mode or a fast exit mode. when entering prechar ge power-down mode, the dll is turned off in slow exit mode or kept on in fast exit mode. the dll remains on when entering active po wer-down as well. odt has special timing constraints when slow exit mode precharge power-down is enabled and entered. refer to ?asynchronous odt mode? on page 172 for detailed odt usage requirements in slow exit mode precharge power-down. a summary of the two power-down modes is listed in table 74 on page 152. table 73: command to power-down entry parameters dram status last command prior to cke low 1 parameter (min) parameter value figure idle or active activate t actpden 1 t ck figure 105 on page 156 idle or active precharge t prpden 1 t ck figure 106 on page 156 active read or readap t rdpden rl + 4 t ck + 1 t ck figure 101 on page 154 active write: bl8otf, bl8mrs, bc4otf t wrpden wl + 4 t ck + t wr/ t ck figure 102 on page 154 active write: bc4mrs wl + 2 t ck + t wr/ t ck figure 102 on page 154 active writeap: bl8otf, bl8mrs, bc4otf t wrapden wl + 4 t ck + wr + 1 t ck figure 103 on page 155 active writeap: bc4mrs wl + 2 t ck + wr + 1 t ck figure 103 on page 155 idle refresh t refpden 1 t ck figure 104 on page 155 power-down refresh t xpdll greater of 10 t ck or 24ns figure 108 on page 157 idle mode register set t mrspden t mod figure 107 on page 157
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 152 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations while in either power-down state, cke is he ld low, reset# is held high, and a stable clock signal must be maintained. odt must be in a valid state but all other input signals are a ?don?t care.? if reset# goes low during power-down, the dram will switch out of power-down mode and go into the reset stat e. after cke is registered low, cke must remain low until t pd (min) has been satisfied. the maximum time allowed for power- down duration is t pd (max) (9 t refi). the power-down states are synchronously exited when cke is registered high (with a required nop or des command). cke must be maintained high until t cke has been satisfied. a valid, executable command may be applied after power-down exit latency, t xp t xpdll have been satisfied. a summary of the power-down modes is listed in tabl e 74 . for certain cke-intensive operations, for ex ample, repeating a power-down exit to refresh to power-down entry sequence, the number of clock cycles between power-down exit and power-down entry may not be sufficient enough to keep the dll properly updated. in addition to meeting t pd when the refresh command is used in between power-down exit and power-down entry, tw o other conditions must be met. first, t xp must be satisfied before issuing the refresh command. second, t xpdll must be satis- fied before the next power-down may be entered. an example is shown in figure 108 on page 157. figure 98: active power-down entry and exit table 74: power-down modes dram state mr1[12] dll state power-down exit relevant parameters active (any bank open) ?don?t care? on fast t xp to any other valid command precharged (all banks precharged) 1on fast t xp to any other valid command 0offslow t xpdll to commands that re q uire the dll to be locked (read, rdap, or odt on) t xp to any other valid command ck ck# command nop nop nop nop address cke t ck t ch t cl enter power-down mode exit power-down mode don?t care valid valid valid t cpded valid t is t ih t ih t is t0 t1 t2 ta0 ta1 ta2 ta3 ta4 nop t xp t cke (min) indicates a break in time scale t pd
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 153 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations figure 99: precharge power-down (fast-exit mode) entry and exit figure 100: precharge power-down (slow-exit mode) entry and exit notes: 1. any valid command not re q uiring a locked dll. 2. any valid command re q uiring a locked dll. tckemin tckemin ck ck# command nop nop nop nop cke t ck t ch t cl enter power-down mode exit power-down mode t pd valid t cpded t is t ih t is t0 t1 t2 t3 t4 t5 ta0 ta1 nop don?t care indicates a break in time scale t xp t cke (min) ck ck# command nop nop nop cke t ck t ch t cl enter power-down mode exit power-down mode t pd valid 2 valid 1 pre t xpdll t cpded t is t ih t is t0 t1 t2 t3 t4 ta ta1 tb nop don?t care indicates a break in time scale t cke (min) t xp
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 154 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations figure 101: power-down entry after read or read with auto precharge (rdap) figure 102: power-down entry after write notes: 1. cke can go low 2 t ck earlier if bc4mrs. t0 t1 ta0 ta1 ta2 ta3 ta4 ta5 ta 6 ta7 ta8 ta9 don ? t c are transitionin g data ta10 ta11 ta12 nop vali d read/ rdap nop nop nop nop nop nop nop nop nop c k c k# c omman d dq bl8 dq b c 4 dq s , dq s # a dd ress c ke t c pded t i s t pd power- d own or self refresh entry in d i c ates a break in time sc ale t rdpden di n + 3 di n + 1 di n + 2 di n rl = al + c l di n + 3 di n + 2 di n + 1 di n di n + 6 di n + 7 di n + 5 di n + 4 t0 t1 ta0 ta1 ta2 ta3 ta4 ta5 ta 6 ta7 t b 0t b 1 t b 2t b 3t b 4 nop write vali d nop nop nop nop nop nop nop nop nop nop nop c k c k# c omman d dq bl8 dq b c 4 dq s , dq s # a dd ress c ke t c pded power- d own or self refresh entry 1 don ? t c are transitionin g data t wrpden di n + 3 di n + 1 di n + 2 di n t pd in d i c ates a break in time sc ale di n + 3 di n + 2 di n + 1 di n di n + 6 di n + 7 di n + 5 di n + 4 t i s wl = al + c wl t wr
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 155 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations figure 103: power-down entry after write with auto precharge (wrap) notes: 1. t wr is programmed through mr0[11:9] and represents t wr (min)ns/ t ck rounded up to the next integer t ck. 2. cke can go low 2 t ck earlier if bc4mrs. figure 104: refresh to power-down entry notes: 1. after cke goes high during t rfc, cke must remain high until t rfc is satisfied. t0 t1 ta0 ta1 ta2 ta3 ta4 ta5 ta 6 ta7 t b 0t b 1 don ? t c are transitionin g data t b 2t b 3t b 4 nop wrap vali d nop nop nop nop nop nop nop nop nop nop nop c k c k# c omman d dq bl8 dq b c 4 dq s , dq s # a dd ress a10 c ke t pd t wrapden power- d own or self refresh entry 2 s tart internal pre c har g e t c pded t i s in d i c ates a break in time sc ale di n + 3 di n + 2 di n + 1 di n di n + 6 di n + 7 di n + 5 di n + 4 di n + 3 di n + 2 di n + 1 di n wr 1 wl = al + c wl ck ck# command refresh nop nop nop nop valid cke t ck t ch t cl t cpded t refpden t is t0 t1 t2 t3 ta0 ta1 ta2 tb0 t xp (min) t rfc (min) 1 don?t care indicates a break in time scale t cke (min) t pd
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 156 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations figure 105: activate to power-down entry figure 106: precharge to power-down entry tcke ck ck# command address active nop nop cke t ck t ch t cl don?t care t cpded t actpden valid t is t0 t1 t2 t3 t4 t5 t6 t7 t pd ck ck# command address cke t ck t ch t cl don?t care t cpded t prepden t is t0 t1 t2 t3 t4 t5 t6 t7 t pd all/single bank pre nop nop
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 157 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations figure 107: mrs command to power-down entry figure 108: power-down exit to refresh to power-down entry notes: 1. t xp must be satisfied before issuing the command. 2. t xpdll must be satisfied (refer enced to the registra tion of power-down exit) before the next power-down can be entered. ck ck# cke t ck t ch t cl t cpded address t is t0 t1 t2 ta0 ta1 ta2 ta3 ta4 t pd don?t care indicates a break in time scale valid command mrs nop nop nop nop nop t mrspden ck ck# cke t ck t ch t cl enter power-down mode enter power-down mode exit power-down mode t pd t cpded t is t ih t is t0 t1 t2 t3 t4 ta0 ta1 tb0 don?t care indicates a break in time scale command nop nop nop nop refresh nop nop t xpdll 2 t xp 1
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 158 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations reset the reset signal (reset#) is an asynchronous signal that triggers any time it drops low, and there are no restrictions about when it can go low. after reset# goes low, it must remain low for 100ns. during this time, the outputs are disabled, odt (r tt ) turns off (high-z), and the dram resets itself. cke should be brought low prior to reset# being driven high. after reset# goes high, the dram must be reinitialized as though a normal power up were executed (see figure 109 on page 159). all refresh counters on the dram are reset, and data stored in the dram is assumed unknown after reset# has gone low.
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_4.fm - rev. d 8/1/08 en 159 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram operations figure 109: reset sequence c ke r tt ba[2:0] all volta g e supplies vali d an d sta b le hi g h-z dm dq s hi g h-z a dd ress a10 c k c k# t c l c omman d nop t0 ta0 don ? t c are t c l t i s odt dq hi g h-z t b 0 t dllk mr1 with dll enable mr s mr s ba0 = h ba1 = l ba2 = l ba0 = l ba1 = l ba2 = l c o d e c o d e c o d e c o d e vali d vali d vali d vali d normal operation mr2 mr3 mr s mr s ba0 = l ba1 = h ba2 = l ba0 = h ba1 = h ba2 = l c o d e c o d e c o d e c o d e t c 0 t d 0 re s et# s ta b le an d vali d c lo c k vali d vali d dram rea d y for external c omman d s t1 t zq init a10 = h zq c l t i s t ioz vali d vali d vali d s ystem re s et (warm b oot) zq c al mr0 with dll re s et t=10ns (min) t = 100ns (min) in d i c ates a break in time sc ale t = 500s (min) t xpr t mrd t mrd t mrd t mod t (min) = max (10ns, 5 t c k) t c k
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_5.fm - rev. d 8/1/08 en 160 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram on-die termination (odt) on-die termination (odt) odt is a feature that enables the dram to enable/disable and turn on/off termination resistance for each dq, dqs, dqs#, and dm for the x4 and x8 configurations (and tdqs, tdqs# for the x8 configuration, when enabled). odt is applied to each dq, udqs, udqs#, ldqs, ldqs#, udm, and ld m signal for the x16 configuration. the odt feature is designed to improve signal integrity of the memory channel by enabling the dram controller to independently turn on/off the dram?s internal termi- nation resistance for any grouping of dram devices. the odt feat ure is not supported during dll disable mode. a simple functional representation of the dram odt feature is shown in figure 110. the switch is enable d by the internal odt control logic, which uses the external odt ball and other control information. figure 110: on-die termination functional representation of odt the value of r tt (odt termination value) is determin ed by the settings of several mode register bits (see table 78 on page 163). the odt ball is ignored while in self refresh mode (must be turned off prior to self refr esh entry) or if mode registers mr1 and mr2 are programmed to disable odt. odt is comprised of nominal odt and dynamic odt modes and either of these can function in synchronous or asynchronous mode (when the dll is off during precharge power-down or when the dll is synchronizing). nominal odt is the base termination and is used in any allowable odt state. dynamic odt is applied only during writes an d provides otf switching from no r tt or r tt _ nom to r tt _ wr . the actual effective termination, r tt _ eff , may be different from the r tt targeted due to nonlinearity of the termination. for r tt _ eff values and calculations, see "odt charac- teristics" on page 49. nominal odt odt (nom) is the base termination resistance for each applicable ball, it is enabled or disabled via mr1[9, 6, 2] (see figure 47 on page 61), and it is turned on or off via the odt ball (see table 75 on page 161). odt v dd q/2 r tt s wit c h dq, dq s , dq s #, dm, tdq s , tdq s # to other c ir c uitry su c h as r c v, . . .
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_5.fm - rev. d 8/1/08 en 161 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram on-die termination (odt) notes: 1. assumes dynamic odt is disabled (see "dynamic odt" on page 162 when enabled). 2. odt is enabled and active during most writes for proper termination, bu t it is not illegal to have it off during writes. 3. odt must be disabled during reads. the r tt _ nom value is restricted during writes. dynamic odt is applicable if enabled. nominal odt resistance r tt _ nom is defined by mr1[9, 6, 2], as shown in figure 47 on page 61. the r tt _ nom termination value applies to the output pins previously mentioned. ddr3 sdram supports multiple r tt _ nom values based on rzq/ n where n can be 2, 4, 6, 8, or 12 and rzq is 240 . r tt _ nom termination is allowed any time after the dram is initialized, calibrated, and not performing read access or when it is not in self refresh mode. write accesses use r tt _ nom if dynamic odt (r tt _ wr ) is disabled. if r tt _ nom is used during writes, only rzq/2, rzq/4, and rzq/ 6 are allowed (see table 78 on page 163). odt timings are summarized in table 76, as well as listed in table 53 on page 67. examples of nominal odt timing are shown in conjunction with the synchronous mode of operation in ?synchronous odt mode? on page 167. table 75: truth table ? odt (nominal) note 1 applies to the entire table mr1[9, 6, 2] odt pin dram termination state dram state notes 000 0 r tt _ nom disabled, odt off any valid 2 000 1 r tt _ nom disabled, odt on any valid ex cept self refresh, read 3 000?101 0 r tt _ nom enabled, odt off any valid 2 000?101 1 r tt _ nom enabled, odt on any valid except self refresh, read 3 110 and 111 x r tt _ nom reserved, odt on or off illegal table 76: odt parameter symbol description begins at defined to definition for all ddr3 speed bins units odtl on odt synchronous turn on delay odt registered high r tt _ on t aon cwl+al-2 t ck odtl off odt synchronous turn off delay odt registered high r tt _ off t aof cwl+al-2 t ck t aonpd odt asynchronous turn on delay odt registered high r tt _ on 1?9 ns t aofpd odt asynchronous turn off delay odt registered high r tt _ off 1?9 ns odth4 odt minimum high time after odt assertion or write (bc4) odt registered high or write registration with odt high odt registered low 4 t ck t ck odth8 odt minimum high time after write (bl8) write registration with odt high odt registered low 6 t ck t ck t aon odt turn-on relative to odtl on completion completion of odtl on r tt _ on see table 53 on page 67 ps t aof odt turn-off relative to odtl off completion completion of odtl off r tt _ off 0.5 t ck 0.2 t ck t ck
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_5.fm - rev. d 8/1/08 en 162 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram on-die termination (odt) dynamic odt in certain application cases, and to further enha nce signal integrity on the data bus, it is desirable that the termination strength of the ddr3 sdram can be changed without issuing an mrs command, essentially changi ng the odt termination on the fly. with dynamic odt (r tt _ wr ) enabled, the dram switches from nominal odt (r tt _ nom ) to dynamic odt (r tt _ wr ) when beginning a write burst and subsequently switches back to nominal odt (r tt _ nom ) at the completion of the write burst. this requirement is supported by the dynamic odt feature, as described below: functional description the dynamic odt mode is enabled if either mr2[9] or mr2[10] is set to ?1.? dynamic odt is not supported during dll disable mode so r tt _ wr must be disabled. the dynamic odt function is described, as follows: ?two r tt values are available?r tt _ nom and r tt _ wr : ?the value for r tt _ nom is preselected via mr1[9, 6, 2] ?the value for r tt _ wr is preselected via mr2[10, 9] ? during dram operation without read or write commands, the termination is controlled as follows: ? nominal termination strength r tt _ nom is used ? termination on/off timing is controlled via the odt ball and latencies odtl on and odtl off ? when a write command (wr, wrap, wrs4, wrs8, wraps4, wraps8) is registered, and if dynamic odt is enabled, the odt termination is controlled as follows: ?a latency of odtl cnw after the write command: termination strength r tt _ nom switches to r tt _ wr ?a latency of odtl cwn 8 (for bl8, fixed or otf) or odtl cwn 4 (for bc4, fixed or otf) after the write command: termination strength r tt _ wr switches back to r tt _ nom ? on/off termination timing is controlled via the odt ball and determined by odtl on, odtl off, odth4, and odth8 ?during the t adc transition window, the value of r tt is undefined odt is constrained during writes and when dynamic odt is enabled (see table 77). odt timings listed in table 76 on page 161 also apply to dynamic odt mode. table 77: dynamic odt specific parameters symbol description begins at defined to definition for all ddr3 speed bins units odtl cnw change from r tt _ nom to r tt _ wr write registration r tt switched from r tt _ nom to r tt _ wr wl - 2 t ck odtl cwn 4 change from r tt _ wr to r tt _ nom (bc4) write registration r tt switched from r tt _ wr to r tt _ nom 4 t ck + odtl off t ck odtl cwn 8 change from r tt _ wr to r tt _ nom (bl8) write registration r tt switched from r tt _ wr to r tt _ nom 6 t ck + odtl off t ck t adc r tt change skew odtl cnw completed r tt transition complete 0.5 t ck 0.2 t ck tck
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_5.fm - rev. d 8/1/08 en 163 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram on-die termination (odt) notes: 1. rzq = 240 . if r tt _ nom is used during writes, only rzq/2, rzq/4, rzq/6 are allowed . table 78: mode registers for r tt _ nom mr1 (r tt _ nom ) r tt _ nom (rzq) r tt _ nom (ohms) r tt _ nom mode restriction m9 m6 m2 000 off off n/a 0 0 1 rzq/4 60 self refresh 0 1 0 rzq/2 120 0 1 1 rzq/6 40 100 rzq/12 20 self refresh, write 1 0 1 rzq/8 30 1 1 0 reserved reserved n/a 1 1 1 reserved reserved n/a table 79: mode registers for r tt _ wr mr2 (r tt _ wr ) r tt _ wr (rzq) r tt _ wr (ohms) m10 m9 0 0 dynamic odt off: writ e does not affect r tt _ nom 01 rzq/4 60 10 rzq/2 120 1 1 reserved reserved n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a table 80: timing diagrams for dynamic odt figure and page title figure 111 on page 164 dynamic odt: odt as serted before and af ter the write, bc4 figure 112 on page 164 dynamic odt: without write command figure 113 on page 165 dynamic odt: odt pin asserted together with write command for 6 clock cycles, bl8 figure 114 on page 166 dynamic odt: odt pin assert ed with write command for 6 clock cycles, bc4 figure 115 on page 166 dynamic odt: odt pin assert ed with write command for 4 clock cycles, bc4
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_5.fm - rev. d 8/1/08 en 164 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram on-die termination (odt) figure 111: dynamic odt: odt asserted before and after the write, bc4 notes: 1. via mrs or otf. al = 0, cwl = 5. r tt _ nom and r tt _ wr are enabled. 2. odth4 applies to first registering odt high and then to the registration of the write command. in this example, odth4 is satisfied if odt goes low at t8 (four clocks afte r the write command). figure 112: dynamic odt: without write command notes: 1. al = 0, cwl = 5. r tt _ nom is enabled and r tt _ wr is either enab led or disabled. 2. odth4 is defined from odt registered high to odt registered low; in this example, odth4 is satisfied. odt registered low at t5 is also legal. t0 t1 t2 t3 t4 t5 t 6 t7 t8 t9 odtl on odtl c wn 4 odtl c nw wl odtl off t10 t11 t12 t13 t14 t15 t17 t1 6 c k c k# c omman d a dd ress r tt odt dq dq s , dq s # vali d wr s 4 nop nop nop nop nop nop nop don ? t c are transitionin g r tt _ wr r tt _ nom r tt _ nom di n + 3 di n + 2 di n + 1 di n nop nop nop nop nop nop nop nop nop nop odth4 odth4 t aon (min) t ad c (min) t ad c (min) t aof (min) t aon (max) t ad c (max) t ad c (max) t aof (max) t0 t1 t2 t3 t4 t5 t 6 t7 t8 t9 odtl off t10 t11 c k c k# r tt don ? t c are transitionin g c omman d vali d vali d vali d vali d vali d vali d vali d vali d vali d vali d vali d vali d a dd ress dq s , dq s # dq odth4 odtl on t aon (max) t aon (min) t aof (min) t aof (max) odt r tt _ nom
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_5.fm - rev. d 8/1/08 en 165 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram on-die termination (odt) figure 113: dynamic odt: odt pin asserted together with write command for 6 clock cycles, bl8 notes: 1. via mrs or otf; al = 0, cwl = 5. if r tt _ nom can be either enabled or disabled, odt can be high. r tt _ wr is enabled. 2. in this example, odth8 = 6 is satisfied exactly. t0 t1 t2 t3 t4 t5 t 6 t7 t8 t9 odtl c wn 8 odtl on odtl c nw wl t aof (max) t10 t11 c k c k# a dd ress r tt odt dq dq s , dq s # di b + 3 di b + 2 di b + 1 di b di b + 7 di b + 6 di b + 5 di b + 4 vali d don ? t c are transitionin g c omman d wr s 8 nop nop nop nop nop nop nop nop nop nop nop r tt _ wr odth8 odtl off t ad c (max) t aon (min) t aof (min)
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_5.fm - rev. d 8/1/08 en 166 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram on-die termination (odt) figure 114: dynamic odt: odt pin asserted with write command for 6 clock cycles, bc4 notes: 1. via mrs or otf. al = 0, cwl = 5. r tt _ nom and r tt _ wr are enabled. 2. odth4 is defined from odt registered high to odt registered low, so in this example, odth4 is satisfied. odt registe red low at t5 is also legal. figure 115: dynamic odt: odt pin asserted with write command for 4 clock cycles, bc4 notes: 1. via mrs or otf. al = 0, cwl = 5. r tt _ nom can be either enabled or disabled. if disabled, odt can remain high. r tt _ wr is enabled. 2. in this example odth4 = 4 is satisfied exactly. t0 t1 t2 t3 t4 t5 t 6 t7 t8 t9 odtl on odtl c nw wl t10 t11 c k c k# odtl c wn 4 dq s , dq s # a dd ress vali d don ? t c are transitionin g odtl off c omman d wr s 4 nop nop nop nop nop nop nop nop nop nop nop dq di n + 3 di n + 2 di n + 1 di n t ad c (min) t aof (min) t aof (max) t ad c (max) t ad c (max) t aon (min) odth4 odt r tt r tt _ wr r tt _ nom t0 t1 t2 t3 t4 t5 t 6 t7 t8 t9 odtl on odtl c nw wl t10 t11 c k c k# odtl c wn 4 dq s , dq s # a dd ress vali d r tt _ wr c omman d wr s 4 nop nop nop nop nop nop nop nop nop nop nop don ? t c are transitionin g dq di n di n + 3 di n + 2 di n + 1 odth4 t ad c (max) t aon (min) t aof (min) t aof (max) odtl off r tt r tt _ wr odt
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_5.fm - rev. d 8/1/08 en 167 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram on-die termination (odt) synchronous odt mode synchronous odt mode is selected whenever the dll is turned on and locked and when either r tt _ nom or r tt _ wr is enabled. based on the power-down definition, these modes are: ? any bank active with cke high ?refresh mode with cke high ? idle mode with cke high ? active power-down mode (regardless of mr0[12]) ? precharge power-down mode if dll is enabled during precharge power-down by mr0[12] odt latency and posted odt in synchronous odt mode, r tt turns on odtl on clock cy cles after odt is sampled high by a rising clock edge and turns off odtl off clock cycles after odt is registered low by a rising clock edge. the actual on/off times varies by t aon and t aof around each clock edge (see table 81 on page 168). the odt latency is tied to the write latency (wl) by odtl on = wl - 2 and odtl off = wl - 2. since write latency is made up of cas writ e latency (cwl) and additive latency (al), the al programmed into the mode register (mr1[4, 3]) also applies to the odt signal. the dram?s internal odt signal is delayed a number of clock cycles defined by the al relative to the external odt signal . thus odtl on = cwl + al - 2 and odtl off = cwl + al - 2. timing parameters synchronous odt mode uses the following timing parameters: odtl on, odtl off, odth4, odth8 , t aon, and t aof (see table 81 and figure 116 on page 168). the minimum r tt turn-on time ( t aon [min]) is the point at which the device leaves high-z and odt resistance begins to turn on. maximum r tt turn-on time ( t aon [max]) is the point at which odt resistance is fully on. bo th are measured relative to odtl on. the minimum r tt turn-off time ( t aof [min]) is the point at which the device starts to turn off odt resistance. maximum r tt turn off time ( t aof [max]) is the point at which odt has reached high-z. both are measured from odtl off. when odt is asserted, it must remain hi gh until odth4 is satisfied. if a write command is registered by the dram with odt high, then odt must remain high until odth4 (bc4) or odth8 (bl8) after the write command (see figure 117 on page 169). odth4 and odth8 are measured from odt registered high to odt regis- tered low or from the registration of a write command until odt is registered low.
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_5.fm - rev. d 8/1/08 en 168 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram on-die termination (odt) figure 116: synchronous odt notes: 1. al = 3; cwl = 5; odtl on = wl = 6.0; odtl off = wl - 2 = 6. r tt _ nom is enabled. table 81: synchronous odt parameters symbol description begins at defined to definition for all ddr3 speed bins units odtl on odt synchronous turn-o n delay odt registered high r tt _ on t aon cwl+al-2 t ck odtl off odt synchronous turn-off delay odt registered high r tt _ off t aof cwl+al-2 t ck odth4 odt minimum high time after odt assertion or write (bc4) odt registered high, or write registration with odt high odt registered low 4 t ck t ck odth8 odt minimum high time after write (bl8) write registration with odt high odt registered low 6 t ck t ck t aon odt turn-on relative to odtl on completion completion of odtl on r tt _ on see table 53 on page 67 ps t aof odt turn-off relative to odtl off completion completion of odtl off r tt _ off 0.5 t ck 0.2 t ck tck t0 t1 t2 t3 t4 t5 t 6 t7 t8 t9 c wl - 2 al = 3 al = 3 t aon (max) t aof (max) t10 t11 t12 t13 t14 t15 c k c k# r tt odt don ? t c are transitionin g r tt _ nom c ke t aof (min) odtl off = c wl + al - 2 odtl on = c wl + al - 2 odth4 (min) t aon (min)
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_5.fm - rev. d 8/1/08 en 169 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram on-die termination (odt) figure 117: synchronous odt (bc4) notes: 1. wl = 7. r tt _ nom is enabled. r tt _ wr is disabled. 2. odt must be held high for at least odth4 after assertion (t1). 3. odt must be kept high odth4 (bc4) or odth8 (bl8) after the write command (t7). 4. odth is measured from odt first registered high to od t first registered low or from the registration of the write command with odt high to odt registered low. 5. although odth4 is satisfied from odt registered high at t6, odt must not go low before t11 as odth4 must also be satisfied from the registration of the write command at t7. t0 t1 t2 t3 t4 t5 t 6 t7 t8 t9 t aof (max) t aof (min) t aon (max) t aof (max) t10 t11 t12 t13 t14 t15 t17 t1 6 c k c k# r tt c ke nop wr s 4 nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop c omman d don ? t c are transitionin g t aon (min) r tt _ nom odtloff = wl - 2 odth4 (min) odth4 odtl off = wl - 2 odtl on = wl - 2 t aon (min) t aon (max) odth4 odtl on = wl - 2 t aof (min) odt r tt _ nom
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_5.fm - rev. d 8/1/08 en 170 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram on-die termination (odt) odt off during reads as the ddr3 sdram cannot terminate and drive at the same time, r tt must be disabled at least one-half clock cycle before the read preamble by driving the odt ball low (if either r tt _ nom or r tt _ wr is enabled). r tt may not be enabled until the end of the post- amble as shown in the example in figure 118 on page 171. note: odt may be disabled earlier and enabled la ter than shown in figure 118 on page 171.
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_5.fm - rev. d 8/1/08 en 171 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram on-die termination (odt) figure 118: odt during reads notes: 1. odt must be disabled ex ternally during reads by driving odt low. for example, cl = 6; al = cl - 1 = 5; rl = al + cl = 11; cwl = 5; odtl on = cwl + al - 2 = 8; odtl off = cwl + al - 2 = 8. r tt _ nom is enabled. r tt _ wr is a ?don?t care.? t0 t1 t2 t3 t4 t5 t 6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t17 t1 6 c k c k# vali d a dd ress di b + 3 di b + 2 di b + 1 di b di b + 7 di b + 6 di b + 5 di b + 4 dq dq s , dq s # don ? t c are transitionin g c omman d nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop read odtl on = c wl + al - 2 odt t aon (max) rl = al + c l odtl off = c wl + al - 2 t aof (min) r tt r tt _ nom r tt _ nom t aof (max)
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_5.fm - rev. d 8/1/08 en 172 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram on-die termination (odt) asynchronous odt mode asynchronous odt mode is available when the dram runs in dll on mode and when either r tt _ nom or r tt _ wr is enabled; however, the dll is temporarily turned off in precharged power-down standby (via mr0[12]). additionally, odt operates asynchro- nously when the dll is synchronizing after being reset. see "power-down mode" on page 151 for definition and guidance over power-down details. in asynchronous odt timing mode, the internal odt command is not delayed by al relative to the external odt command. in asynchronous odt mode, odt controls r tt by analog time. the timing parameters t aonpd and t aofpd (see table 82 on page 173) replace odtl on/ t aon and odtl off/ t aof, respectively, when odt operates asyn- chronously (see figure 119 on page 173). the minimum r tt turn-on time ( t aonpd [min]) is the point at which the device termi- nation circuit leaves high-z and odt resistance begins to turn on. maximum r tt turn- on time ( t aonpd [max]) is the point at which odt resistance is fully on. t aonpd (min) and t aonpd (max) are measured from odt being sampled high. the minimum r tt turn-off time ( t aofpd [min]) is the point at which the device termi- nation circuit starts to turn off odt resistance. maximum r tt turn-off time ( t aofpd [max]) is the point at which odt has reached high-z. t aofpd (min) and t aofpd (max) are measured from odt being sampled low.
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_5.fm - rev. d 8/1/08 en 173 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram on-die termination (odt) figure 119: asynchronous odt timing with fast odt transition notes: 1. al is ignored. table 82: asynchronous odt timing parameters for all speed bins symbol description min max units t aonpd asynchronous r tt turn-on delay (power-down with dll off) 1 9 ns t aofpd asynchronous r tt turn-off delay (power-down with dll off) 1 9 ns t0 t1 t2 t3 t4 t5 t 6 t7 t8 t9 t aonpd (max) t aofpd (max) t10 t11 t12 t13 t14 t15 t17 t1 6 c k c k# r tt odt r tt _ nom don ? t c are transitionin g c ke t ih t i s t ih t i s t aofpd (min) t aonpd (min)
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_5.fm - rev. d 8/1/08 en 174 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram on-die termination (odt) synchronous to asynchronous odt mode transition (power-down entry) there is a transition period around powe r-down entry (pde) where the dram?s odt may exhibit either synchronou s or asynchronous behavior . this transition period occurs if the dll is selected to be off when in precharge power-down mode by the setting mr0[12] = 0. power-down entry begins t anpd prior to cke first being registered low, and it ends when cke is first registered low. t anpd is equal to the greater of odtl off + 1 t ck or odtl on + 1 t ck. if a refresh command has been issued, and it is in progress when cke goes low, power-down entry will end t rfc after the refresh command rather than when cke is first registered low. power-down entry will then become the greater of t anpd and t rfc - refresh command to cke registered low. odt assertion during power-down entry results in an r tt change as early as the lesser of t aonpd (min) and odtl on t ck + t aon (min) or as late as the greater of t aonpd (max) and odtl on t ck + t aon (max). odt de-assertion during power-down entry may result in an r tt change as early as the lesser of t aofpd (min) and odtl off t ck + t aof (min) or as late as the greater of t aofpd (max) and odtl off t ck + t aof (max). table 83 on page 175 summarizes these parameters. if the al has a large value, the uncertainty of the state of r tt becomes quite large. this is because odtl on and odtl off are derived from the wl and wl is equal to cwl + al. figure 120 on page 175 shows three different cases: ? odt_a: synchronous behavior before t anpd ? odt_b: odt state changes during the transition period with t aonpd (min) less than odtl on t ck + t aon (min) and t aonpd (max) greater than odtl on t ck + t aon (max) ? odt_c: odt state changes after the transi tion period with asynchronous behavior
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_5.fm - rev. d 8/1/08 en 175 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram on-die termination (odt) figure 120: synchronous to asynchronous transition during precharge power-down (dll off) entry notes: 1. al = 0; cwl = 5; odtl off = wl - 2 = 3. table 83: odt parameters for power-down (dll off) entry and exit transition period description min max power-down entry transition period (power-down entry) greater of: t anpd or t rfc - refresh to cke low power-down exit transition period (power-down exit) t anpd + t xpdll odt to r tt turn-on delay (odtl on = wl - 2) lesser of: t aonpd (min) (1ns) or odtl on t ck + t aon (min) greater of: t aonpd (max) (9ns) or odtl on t ck + t aon (max) odt to r tt turn-off delay (odtl off = wl - 2) lesser of: t aofpd (min) (1ns) or odtl off t ck + t aof (min) greater of: t aofpd (max) (9ns) or odtl off t ck + t aof (max) t anpd wl - 1 (greater of odtl off + 1 or odtl on + 1) t0 t1 t2 t3 t4 t5 t 6 t7 t8 t9 t aofpd (max) odtl off t10 t11 t12 t13 ta0 ta1 ta3 ta2 c k c k# dram r tt b asyn c hronous or syn c hronous r tt _ nom dram r tt c asyn c hronous r tt _ nom don ? t c are transitionin g c ke nop nop nop nop nop c omman d nop ref nop nop nop nop nop nop nop nop nop nop nop pde transition perio d in d i c ates a break in time sc ale odtl off + t aofpd (min) t aofpd (max) t aofpd (min) odtl off + t aofpd (max) t aofpd (min) t anpd t aof (min) t aof (max) dram r tt a syn c hronous r tt _ nom odt a syn c hronous odt c asyn c hronous odt b asyn c hronous or syn c hronous t rf c (min)
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_5.fm - rev. d 8/1/08 en 176 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram on-die termination (odt) asynchronous to synchronous odt mode transition (power-down exit) the dram?s odt may exhibit either asynch ronous or synchronous behavior during power-down exit (pdx). this transition period occurs if the dll is selected to be off when in precharge power-down mode by setting mr0[12] to ?0.? power-down exit begins t anpd prior to cke first being registered high, and it ends t xpdll after cke is first registered high. t anpd is equal to the greater of odtl off + 1 t ck or odtl on + 1 t ck. the transition period is t anpd plus t xpdll. odt assertion during power-down exit results in an r tt change as early as the lesser of t aonpd (min) and odtl on t ck + t aon (min) or as late as the greater of t aonpd (max) and odtl on t ck + t aon (max). odt de-assertion during power- down exit may result in an r tt change as early as the lesser of t aofpd (min) and odtl off t ck + t aof (min) or as late as the greater of t aofpd (max) and odtl off t ck + t aof (max). table 83 on page 175 summarizes these parameters. if the al has a large value, the uncertainty of the r tt state becomes quite large. this is because odtl on and odtl off are derived from the wl, and wl is equal to cwl + al. figure 121 on page 177 shows three different cases: ? odt c: asynchronous behavior before t anpd ? odt b: odt state changes during the transition period, with t aofpd (min) less than odtl off t ck + t aof (min) and odtl off t ck + t aof (max) greater than t aofpd (max) ? odt a: odt state changes after the transition period with synchronous response
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_5.fm - rev. d 8/1/08 en 177 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram on-die termination (odt) figure 121: asynchronous to synchronous transition during precharge power-down (dll off) exit notes: 1. cl = 6; al = cl - 1; cwl = 5; odtl off = wl - 2 = 8. t0 t1 t2 ta0 ta1 ta2 ta3 ta4 ta5 ta 6 t b 0 t b 1 t b 2 t c 0 t c 1 t d 0 t d 1 t c 2 c k c k# don ? t c are transitionin g odt c syn c hronous nop nop nop c ommand nop nop nop nop nop nop nop nop nop r tt b asyn c hronous or syn c hronous dram r tt a asyn c hronous dram r tt c syn c hronous r tt _ nom nop nop odt b asyn c hronous or syn c hronous c ke t aof (min) r tt _ nom in d i c ates a break in time sc ale odtl off + t aof (min) t aofpd (max) odtl off + t aof (max) t xpdll t aof (max) odtl off odt a asyn c hronous pdx transition perio d t aofpd (min) t aofpd (max) t anpd t aofpd (min) r tt _ nom
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_5.fm - rev. d 8/1/08 en 178 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram on-die termination (odt) asynchronous to synchronous odt mode transition (short cke pulse) if the time in the precharge power down or idle states is very short (short cke low pulse), the power-down entry and power-down exit transition periods will overlap. when overlap occurs, the response of the dram?s r tt to a change in the odt state may be synchronous or asynchronous from the start of the power-down entry transition period to the end of the power-down exit transition period even if the entry period ends later than the exit period (see figure 122 on page 179). if the time in the idle state is very short (short cke high pulse), the power-down exit and power-down entry transition periods overlap. when this overlap occurs, the response of the dram?s r tt to a change in the odt state may be synchronous or asyn- chronous from the start of power-down exit transition period to the end of the power- down entry transition period (see figure 122 on page 179).
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_5.fm - rev. d 8/1/08 en 179 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram on-die termination (odt) figure 122: transition period for short cke low cycles with entry and exit period overlapping notes: 1. al = 0, wl = 5, t anpd = 4. t0 t1 t2 t3 t4 t5 t 6 t7 t8 t9 ta0 ta1 ta2 ta3 ta4 c k c k# c ke c omman d don ? t c are transitionin g t xpdll t rf c (min) nop nop nop nop nop nop nop nop nop nop ref nop nop nop nop pde transition perio d pdx transition perio d in d i c ates a break in time sc ale t anpd s hort c ke low transition perio d (r tt c han g e asyn c hronous or syn c hronous) t anpd
pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr3_5.fm - rev. d 8/1/08 en 180 ?2006 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr3 sdram on-die termination (odt) figure 123: transition period for short cke high cycles with entry and exit period overlapping notes: 1. al = 0, wl = 5, t anpd = 4. t0 t1 t2 t3 t4 t5 t 6 t7 t8 t9 c k c k# c omman d don ? t c are transitionin g nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop t anpd t xpdll in d i c ates a break in time sc ale ta0 ta1 ta2 ta3 ta4 c ke s hort c ke hi g h transition perio d (r tt c han g e asyn c hronous or syn c honous) t anpd
8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 prodmktg@micron.com www.micron.com customer comment line: 800-932-4992 micron, the m logo, and the micron logo ar e trademarks of micron technology, inc. all other trademarks are the property of thei r respec- tive owners. this data sheet contains minimum and maximum limits specified ov er the power supply and temperat ure range set forth herein. alt hough considered final, these specifications are subject to change, as further product development and data characterization sometime s occur. 1gb: x4, x8, x16 ddr3 sdram on-die termination (odt) pdf: 09005aef826aa906/source: 09005aef82a357c3 micron technology, inc., reserves the right to change products or specifications without notice. ddr3_5.fm - rev d 8/1/08 en 181 ?2006 micron technology, inc. all rights reserved.

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